1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
4  */
5 
6 #include <asm/arch/clock.h>
7 #include <asm/arch/iomux.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/crm_regs.h>
10 #include <asm/arch/mx6ul_pins.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/gpio.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <asm/io.h>
18 #include <common.h>
19 #include <fsl_esdhc.h>
20 #include <i2c.h>
21 #include <miiphy.h>
22 #include <linux/sizes.h>
23 #include <mmc.h>
24 #include <netdev.h>
25 #include <power/pmic.h>
26 #include <power/pfuze3000_pmic.h>
27 #include "../common/pfuze.h"
28 #include <usb.h>
29 #include <usb/ehci-ci.h>
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
34 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
35 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
36 
37 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
38 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
39 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
40 
41 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	\
42 	PAD_CTL_PUS_100K_DOWN  | PAD_CTL_SPEED_LOW |		\
43 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
44 
45 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
46 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
47 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
48 	PAD_CTL_ODE)
49 
50 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
51 	PAD_CTL_SPEED_HIGH   |                                  \
52 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
53 
54 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
55 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
56 
57 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
58 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
59 
60 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
61 
62 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
63 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
64 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
65 
66 #ifdef CONFIG_DM_PMIC
67 int power_init_board(void)
68 {
69 	struct udevice *dev;
70 	int ret, dev_id, rev_id;
71 	unsigned int reg;
72 
73 	ret = pmic_get("pfuze3000", &dev);
74 	if (ret == -ENODEV)
75 		return 0;
76 	if (ret != 0)
77 		return ret;
78 
79 	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
80 	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
81 	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
82 
83 	/* disable Low Power Mode during standby mode */
84 	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
85 	reg |= 0x1;
86 	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
87 
88 	/* SW1B step ramp up time from 2us to 4us/25mV */
89 	pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
90 
91 	/* SW1B mode to APS/PFM */
92 	pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
93 
94 	/* SW1B standby voltage set to 0.975V */
95 	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
96 
97 	return 0;
98 }
99 #endif
100 
101 int dram_init(void)
102 {
103 	gd->ram_size = imx_ddr_size();
104 
105 	return 0;
106 }
107 
108 static iomux_v3_cfg_t const uart1_pads[] = {
109 	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
110 	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
111 };
112 
113 #ifndef CONFIG_SPL_BUILD
114 static iomux_v3_cfg_t const usdhc1_pads[] = {
115 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 
122 	/* VSELECT */
123 	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 	/* CD */
125 	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
126 	/* RST_B */
127 	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
128 };
129 #endif
130 
131 /*
132  * mx6ul_14x14_evk board default supports sd card. If want to use
133  * EMMC, need to do board rework for sd2.
134  * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
135  * emmc, need to define this macro.
136  */
137 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
138 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
139 	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 
150 	/*
151 	 * RST_B
152 	 */
153 	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
154 };
155 #else
156 static iomux_v3_cfg_t const usdhc2_pads[] = {
157 	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 };
164 
165 /*
166  * The evk board uses DAT3 to detect CD card plugin,
167  * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
168  */
169 static iomux_v3_cfg_t const usdhc2_cd_pad =
170 	MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
171 
172 static iomux_v3_cfg_t const usdhc2_dat3_pad =
173 	MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
174 	MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
175 #endif
176 
177 static void setup_iomux_uart(void)
178 {
179 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
180 }
181 
182 #ifdef CONFIG_FSL_QSPI
183 static int board_qspi_init(void)
184 {
185 	/* Set the clock */
186 	enable_qspi_clk(0);
187 
188 	return 0;
189 }
190 #endif
191 
192 #ifdef CONFIG_FSL_ESDHC
193 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
194 	{USDHC1_BASE_ADDR, 0, 4},
195 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
196 	{USDHC2_BASE_ADDR, 0, 8},
197 #else
198 	{USDHC2_BASE_ADDR, 0, 4},
199 #endif
200 };
201 
202 #define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
203 #define USDHC1_PWR_GPIO	IMX_GPIO_NR(1, 9)
204 #define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 5)
205 #define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 10)
206 
207 int board_mmc_getcd(struct mmc *mmc)
208 {
209 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
210 	int ret = 0;
211 
212 	switch (cfg->esdhc_base) {
213 	case USDHC1_BASE_ADDR:
214 		ret = !gpio_get_value(USDHC1_CD_GPIO);
215 		break;
216 	case USDHC2_BASE_ADDR:
217 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
218 		ret = 1;
219 #else
220 		imx_iomux_v3_setup_pad(usdhc2_cd_pad);
221 		gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
222 		gpio_direction_input(USDHC2_CD_GPIO);
223 
224 		/*
225 		 * Since it is the DAT3 pin, this pin is pulled to
226 		 * low voltage if no card
227 		 */
228 		ret = gpio_get_value(USDHC2_CD_GPIO);
229 
230 		imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
231 #endif
232 		break;
233 	}
234 
235 	return ret;
236 }
237 
238 int board_mmc_init(bd_t *bis)
239 {
240 #ifdef CONFIG_SPL_BUILD
241 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
242 	imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
243 					 ARRAY_SIZE(usdhc2_emmc_pads));
244 #else
245 	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
246 #endif
247 	gpio_direction_output(USDHC2_PWR_GPIO, 0);
248 	udelay(500);
249 	gpio_direction_output(USDHC2_PWR_GPIO, 1);
250 	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
251 	return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
252 #else
253 	int i, ret;
254 
255 	/*
256 	 * According to the board_mmc_init() the following map is done:
257 	 * (U-Boot device node)    (Physical Port)
258 	 * mmc0                    USDHC1
259 	 * mmc1                    USDHC2
260 	 */
261 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
262 		switch (i) {
263 		case 0:
264 			imx_iomux_v3_setup_multiple_pads(
265 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
266 			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
267 			gpio_direction_input(USDHC1_CD_GPIO);
268 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
269 
270 			gpio_direction_output(USDHC1_PWR_GPIO, 0);
271 			udelay(500);
272 			gpio_direction_output(USDHC1_PWR_GPIO, 1);
273 			break;
274 		case 1:
275 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
276 			imx_iomux_v3_setup_multiple_pads(
277 				usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
278 #else
279 			imx_iomux_v3_setup_multiple_pads(
280 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
281 #endif
282 			gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
283 			gpio_direction_output(USDHC2_PWR_GPIO, 0);
284 			udelay(500);
285 			gpio_direction_output(USDHC2_PWR_GPIO, 1);
286 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
287 			break;
288 		default:
289 			printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
290 			return -EINVAL;
291 			}
292 
293 			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
294 			if (ret) {
295 				printf("Warning: failed to initialize mmc dev %d\n", i);
296 				return ret;
297 			}
298 	}
299 #endif
300 	return 0;
301 }
302 #endif
303 
304 #ifdef CONFIG_USB_EHCI_MX6
305 #ifndef CONFIG_DM_USB
306 
307 #define USB_OTHERREGS_OFFSET	0x800
308 #define UCTRL_PWR_POL		(1 << 9)
309 
310 static iomux_v3_cfg_t const usb_otg_pads[] = {
311 	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
312 };
313 
314 /* At default the 3v3 enables the MIC2026 for VBUS power */
315 static void setup_usb(void)
316 {
317 	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
318 					 ARRAY_SIZE(usb_otg_pads));
319 }
320 
321 int board_usb_phy_mode(int port)
322 {
323 	if (port == 1)
324 		return USB_INIT_HOST;
325 	else
326 		return usb_phy_mode(port);
327 }
328 
329 int board_ehci_hcd_init(int port)
330 {
331 	u32 *usbnc_usb_ctrl;
332 
333 	if (port > 1)
334 		return -EINVAL;
335 
336 	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
337 				 port * 4);
338 
339 	/* Set Power polarity */
340 	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
341 
342 	return 0;
343 }
344 #endif
345 #endif
346 
347 #ifdef CONFIG_FEC_MXC
348 /*
349  * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
350  * be used for ENET1 or ENET2, cannot be used for both.
351  */
352 static iomux_v3_cfg_t const fec1_pads[] = {
353 	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
354 	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
355 	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
356 	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
357 	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
358 	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
359 	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
360 	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
361 	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
362 	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
363 };
364 
365 static iomux_v3_cfg_t const fec2_pads[] = {
366 	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
367 	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
368 
369 	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
370 	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
371 	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
372 	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
373 
374 	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
375 	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
376 	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
377 	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
378 };
379 
380 static void setup_iomux_fec(int fec_id)
381 {
382 	if (fec_id == 0)
383 		imx_iomux_v3_setup_multiple_pads(fec1_pads,
384 						 ARRAY_SIZE(fec1_pads));
385 	else
386 		imx_iomux_v3_setup_multiple_pads(fec2_pads,
387 						 ARRAY_SIZE(fec2_pads));
388 }
389 
390 int board_eth_init(bd_t *bis)
391 {
392 	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
393 
394 	return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
395 				       CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
396 }
397 
398 static int setup_fec(int fec_id)
399 {
400 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
401 	int ret;
402 
403 	if (fec_id == 0) {
404 		/*
405 		 * Use 50M anatop loopback REF_CLK1 for ENET1,
406 		 * clear gpr1[13], set gpr1[17].
407 		 */
408 		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
409 				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
410 	} else {
411 		/*
412 		 * Use 50M anatop loopback REF_CLK2 for ENET2,
413 		 * clear gpr1[14], set gpr1[18].
414 		 */
415 		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
416 				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
417 	}
418 
419 	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
420 	if (ret)
421 		return ret;
422 
423 	enable_enet_clk(1);
424 
425 	return 0;
426 }
427 
428 int board_phy_config(struct phy_device *phydev)
429 {
430 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
431 
432 	if (phydev->drv->config)
433 		phydev->drv->config(phydev);
434 
435 	return 0;
436 }
437 #endif
438 
439 #ifdef CONFIG_VIDEO_MXS
440 static iomux_v3_cfg_t const lcd_pads[] = {
441 	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
442 	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
443 	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
444 	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
445 	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
446 	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
447 	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
448 	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
449 	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
450 	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
451 	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
452 	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
453 	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
454 	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
455 	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
456 	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
457 	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
458 	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
459 	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
460 	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
461 	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
462 	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
463 	MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
464 	MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
465 	MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
466 	MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
467 	MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
468 	MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
469 
470 	/* LCD_RST */
471 	MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
472 
473 	/* Use GPIO for Brightness adjustment, duty cycle = period. */
474 	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
475 };
476 
477 static int setup_lcd(void)
478 {
479 	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
480 
481 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
482 
483 	/* Reset the LCD */
484 	gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
485 	gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
486 	udelay(500);
487 	gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
488 
489 	/* Set Brightness to high */
490 	gpio_request(IMX_GPIO_NR(1, 8), "backlight");
491 	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
492 
493 	return 0;
494 }
495 #endif
496 
497 int board_early_init_f(void)
498 {
499 	setup_iomux_uart();
500 
501 	return 0;
502 }
503 
504 int board_init(void)
505 {
506 	/* Address of boot parameters */
507 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
508 
509 #ifdef	CONFIG_FEC_MXC
510 	setup_fec(CONFIG_FEC_ENET_DEV);
511 #endif
512 
513 #ifdef CONFIG_USB_EHCI_MX6
514 #ifndef CONFIG_DM_USB
515 	setup_usb();
516 #endif
517 #endif
518 
519 #ifdef CONFIG_FSL_QSPI
520 	board_qspi_init();
521 #endif
522 
523 #ifdef CONFIG_VIDEO_MXS
524 	setup_lcd();
525 #endif
526 
527 	return 0;
528 }
529 
530 #ifdef CONFIG_CMD_BMODE
531 static const struct boot_mode board_boot_modes[] = {
532 	/* 4 bit bus width */
533 	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
534 	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
535 	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
536 	{NULL,	 0},
537 };
538 #endif
539 
540 int board_late_init(void)
541 {
542 #ifdef CONFIG_CMD_BMODE
543 	add_board_boot_modes(board_boot_modes);
544 #endif
545 
546 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
547 	env_set("board_name", "EVK");
548 
549 	if (is_mx6ul_9x9_evk())
550 		env_set("board_rev", "9X9");
551 	else
552 		env_set("board_rev", "14X14");
553 #endif
554 
555 	return 0;
556 }
557 
558 int checkboard(void)
559 {
560 	if (is_mx6ul_9x9_evk())
561 		puts("Board: MX6UL 9x9 EVK\n");
562 	else
563 		puts("Board: MX6UL 14x14 EVK\n");
564 
565 	return 0;
566 }
567 
568 #ifdef CONFIG_SPL_BUILD
569 #include <linux/libfdt.h>
570 #include <spl.h>
571 #include <asm/arch/mx6-ddr.h>
572 
573 
574 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
575 	.grp_addds = 0x00000030,
576 	.grp_ddrmode_ctl = 0x00020000,
577 	.grp_b0ds = 0x00000030,
578 	.grp_ctlds = 0x00000030,
579 	.grp_b1ds = 0x00000030,
580 	.grp_ddrpke = 0x00000000,
581 	.grp_ddrmode = 0x00020000,
582 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
583 	.grp_ddr_type = 0x00080000,
584 #else
585 	.grp_ddr_type = 0x000c0000,
586 #endif
587 };
588 
589 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
590 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
591 	.dram_dqm0 = 0x00000030,
592 	.dram_dqm1 = 0x00000030,
593 	.dram_ras = 0x00000030,
594 	.dram_cas = 0x00000030,
595 	.dram_odt0 = 0x00000000,
596 	.dram_odt1 = 0x00000000,
597 	.dram_sdba2 = 0x00000000,
598 	.dram_sdclk_0 = 0x00000030,
599 	.dram_sdqs0 = 0x00003030,
600 	.dram_sdqs1 = 0x00003030,
601 	.dram_reset = 0x00000030,
602 };
603 
604 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
605 	.p0_mpwldectrl0 = 0x00000000,
606 	.p0_mpdgctrl0 = 0x20000000,
607 	.p0_mprddlctl = 0x4040484f,
608 	.p0_mpwrdlctl = 0x40405247,
609 	.mpzqlp2ctl = 0x1b4700c7,
610 };
611 
612 static struct mx6_lpddr2_cfg mem_ddr = {
613 	.mem_speed = 800,
614 	.density = 2,
615 	.width = 16,
616 	.banks = 4,
617 	.rowaddr = 14,
618 	.coladdr = 10,
619 	.trcd_lp = 1500,
620 	.trppb_lp = 1500,
621 	.trpab_lp = 2000,
622 	.trasmin = 4250,
623 };
624 
625 struct mx6_ddr_sysinfo ddr_sysinfo = {
626 	.dsize = 0,
627 	.cs_density = 18,
628 	.ncs = 1,
629 	.cs1_mirror = 0,
630 	.walat = 0,
631 	.ralat = 5,
632 	.mif3_mode = 3,
633 	.bi_on = 1,
634 	.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
635 	.rtt_nom = 0,
636 	.sde_to_rst = 0,    /* LPDDR2 does not need this field */
637 	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
638 	.ddr_type = DDR_TYPE_LPDDR2,
639 	.refsel = 0,	/* Refresh cycles at 64KHz */
640 	.refr = 3,	/* 4 refresh commands per refresh cycle */
641 };
642 
643 #else
644 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
645 	.dram_dqm0 = 0x00000030,
646 	.dram_dqm1 = 0x00000030,
647 	.dram_ras = 0x00000030,
648 	.dram_cas = 0x00000030,
649 	.dram_odt0 = 0x00000030,
650 	.dram_odt1 = 0x00000030,
651 	.dram_sdba2 = 0x00000000,
652 	.dram_sdclk_0 = 0x00000030,
653 	.dram_sdqs0 = 0x00000030,
654 	.dram_sdqs1 = 0x00000030,
655 	.dram_reset = 0x00000030,
656 };
657 
658 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
659 	.p0_mpwldectrl0 = 0x00000000,
660 	.p0_mpdgctrl0 = 0x41570155,
661 	.p0_mprddlctl = 0x4040474A,
662 	.p0_mpwrdlctl = 0x40405550,
663 };
664 
665 struct mx6_ddr_sysinfo ddr_sysinfo = {
666 	.dsize = 0,
667 	.cs_density = 20,
668 	.ncs = 1,
669 	.cs1_mirror = 0,
670 	.rtt_wr = 2,
671 	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
672 	.walat = 0,		/* Write additional latency */
673 	.ralat = 5,		/* Read additional latency */
674 	.mif3_mode = 3,		/* Command prediction working mode */
675 	.bi_on = 1,		/* Bank interleaving enabled */
676 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
677 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
678 	.ddr_type = DDR_TYPE_DDR3,
679 	.refsel = 0,	/* Refresh cycles at 64KHz */
680 	.refr = 1,	/* 2 refresh commands per refresh cycle */
681 };
682 
683 static struct mx6_ddr3_cfg mem_ddr = {
684 	.mem_speed = 800,
685 	.density = 4,
686 	.width = 16,
687 	.banks = 8,
688 	.rowaddr = 15,
689 	.coladdr = 10,
690 	.pagesz = 2,
691 	.trcd = 1375,
692 	.trcmin = 4875,
693 	.trasmin = 3500,
694 };
695 #endif
696 
697 static void ccgr_init(void)
698 {
699 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
700 
701 	writel(0xFFFFFFFF, &ccm->CCGR0);
702 	writel(0xFFFFFFFF, &ccm->CCGR1);
703 	writel(0xFFFFFFFF, &ccm->CCGR2);
704 	writel(0xFFFFFFFF, &ccm->CCGR3);
705 	writel(0xFFFFFFFF, &ccm->CCGR4);
706 	writel(0xFFFFFFFF, &ccm->CCGR5);
707 	writel(0xFFFFFFFF, &ccm->CCGR6);
708 	writel(0xFFFFFFFF, &ccm->CCGR7);
709 }
710 
711 static void spl_dram_init(void)
712 {
713 	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
714 	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
715 }
716 
717 void board_init_f(ulong dummy)
718 {
719 	ccgr_init();
720 
721 	/* setup AIPS and disable watchdog */
722 	arch_cpu_init();
723 
724 	/* iomux and setup of i2c */
725 	board_early_init_f();
726 
727 	/* setup GP timer */
728 	timer_init();
729 
730 	/* UART clocks enabled and gd valid - init serial console */
731 	preloader_console_init();
732 
733 	/* DDR initialization */
734 	spl_dram_init();
735 
736 	/* Clear the BSS. */
737 	memset(__bss_start, 0, __bss_end - __bss_start);
738 
739 	/* load/boot image from boot device */
740 	board_init_r(NULL, 0);
741 }
742 #endif
743