1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/iomux.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/mx6ul_pins.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/boot_mode.h> 17 #include <asm/imx-common/mxc_i2c.h> 18 #include <asm/io.h> 19 #include <common.h> 20 #include <fsl_esdhc.h> 21 #include <i2c.h> 22 #include <linux/sizes.h> 23 #include <mmc.h> 24 #include <usb.h> 25 #include <usb/ehci-fsl.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 30 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 31 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 32 33 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 34 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 35 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 37 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 38 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 39 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 40 41 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 42 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 44 PAD_CTL_ODE) 45 46 #define IOX_SDI IMX_GPIO_NR(5, 10) 47 #define IOX_STCP IMX_GPIO_NR(5, 7) 48 #define IOX_SHCP IMX_GPIO_NR(5, 11) 49 #define IOX_OE IMX_GPIO_NR(5, 18) 50 51 static iomux_v3_cfg_t const iox_pads[] = { 52 /* IOX_SDI */ 53 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 54 /* IOX_SHCP */ 55 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 56 /* IOX_STCP */ 57 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 58 /* IOX_nOE */ 59 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 60 }; 61 62 /* 63 * HDMI_nRST --> Q0 64 * ENET1_nRST --> Q1 65 * ENET2_nRST --> Q2 66 * CAN1_2_STBY --> Q3 67 * BT_nPWD --> Q4 68 * CSI_RST --> Q5 69 * CSI_PWDN --> Q6 70 * LCD_nPWREN --> Q7 71 */ 72 enum qn { 73 HDMI_NRST, 74 ENET1_NRST, 75 ENET2_NRST, 76 CAN1_2_STBY, 77 BT_NPWD, 78 CSI_RST, 79 CSI_PWDN, 80 LCD_NPWREN, 81 }; 82 83 enum qn_func { 84 qn_reset, 85 qn_enable, 86 qn_disable, 87 }; 88 89 enum qn_level { 90 qn_low = 0, 91 qn_high = 1, 92 }; 93 94 static enum qn_level seq[3][2] = { 95 {0, 1}, {1, 1}, {0, 0} 96 }; 97 98 static enum qn_func qn_output[8] = { 99 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, 100 qn_disable, qn_enable 101 }; 102 103 static void iox74lv_init(void) 104 { 105 int i; 106 107 gpio_direction_output(IOX_OE, 0); 108 109 for (i = 7; i >= 0; i--) { 110 gpio_direction_output(IOX_SHCP, 0); 111 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 112 udelay(500); 113 gpio_direction_output(IOX_SHCP, 1); 114 udelay(500); 115 } 116 117 gpio_direction_output(IOX_STCP, 0); 118 udelay(500); 119 /* 120 * shift register will be output to pins 121 */ 122 gpio_direction_output(IOX_STCP, 1); 123 124 for (i = 7; i >= 0; i--) { 125 gpio_direction_output(IOX_SHCP, 0); 126 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 127 udelay(500); 128 gpio_direction_output(IOX_SHCP, 1); 129 udelay(500); 130 } 131 gpio_direction_output(IOX_STCP, 0); 132 udelay(500); 133 /* 134 * shift register will be output to pins 135 */ 136 gpio_direction_output(IOX_STCP, 1); 137 138 gpio_direction_output(IOX_OE, 1); 139 }; 140 141 void iox74lv_set(int index) 142 { 143 int i; 144 145 gpio_direction_output(IOX_OE, 0); 146 147 for (i = 7; i >= 0; i--) { 148 gpio_direction_output(IOX_SHCP, 0); 149 150 if (i == index) 151 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 152 else 153 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 154 udelay(500); 155 gpio_direction_output(IOX_SHCP, 1); 156 udelay(500); 157 } 158 159 gpio_direction_output(IOX_STCP, 0); 160 udelay(500); 161 /* 162 * shift register will be output to pins 163 */ 164 gpio_direction_output(IOX_STCP, 1); 165 166 for (i = 7; i >= 0; i--) { 167 gpio_direction_output(IOX_SHCP, 0); 168 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 169 udelay(500); 170 gpio_direction_output(IOX_SHCP, 1); 171 udelay(500); 172 } 173 174 gpio_direction_output(IOX_STCP, 0); 175 udelay(500); 176 /* 177 * shift register will be output to pins 178 */ 179 gpio_direction_output(IOX_STCP, 1); 180 181 gpio_direction_output(IOX_OE, 1); 182 }; 183 184 #ifdef CONFIG_SYS_I2C_MXC 185 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 186 /* I2C1 for PMIC and EEPROM */ 187 struct i2c_pads_info i2c_pad_info1 = { 188 .scl = { 189 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, 190 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, 191 .gp = IMX_GPIO_NR(1, 28), 192 }, 193 .sda = { 194 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, 195 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, 196 .gp = IMX_GPIO_NR(1, 29), 197 }, 198 }; 199 #endif 200 201 int dram_init(void) 202 { 203 gd->ram_size = PHYS_SDRAM_SIZE; 204 205 return 0; 206 } 207 208 static iomux_v3_cfg_t const uart1_pads[] = { 209 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 210 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 211 }; 212 213 static iomux_v3_cfg_t const usdhc1_pads[] = { 214 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 215 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 216 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 217 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 218 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 219 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 220 221 /* VSELECT */ 222 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 223 /* CD */ 224 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 225 /* RST_B */ 226 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 227 }; 228 229 /* 230 * mx6ul_14x14_evk board default supports sd card. If want to use 231 * EMMC, need to do board rework for sd2. 232 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support 233 * emmc, need to define this macro. 234 */ 235 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 236 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { 237 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 238 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 239 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 240 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 241 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 242 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 243 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 244 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 245 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 246 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 247 248 /* 249 * RST_B 250 */ 251 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 252 }; 253 #else 254 static iomux_v3_cfg_t const usdhc2_pads[] = { 255 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 256 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 257 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 258 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 259 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 260 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 261 }; 262 263 static iomux_v3_cfg_t const usdhc2_cd_pads[] = { 264 /* 265 * The evk board uses DAT3 to detect CD card plugin, 266 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. 267 */ 268 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 269 }; 270 271 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { 272 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | 273 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 274 }; 275 #endif 276 277 static void setup_iomux_uart(void) 278 { 279 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 280 } 281 282 #ifdef CONFIG_FSL_QSPI 283 284 #define QSPI_PAD_CTRL1 \ 285 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ 286 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) 287 288 static iomux_v3_cfg_t const quadspi_pads[] = { 289 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 290 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 291 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 292 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 293 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 294 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 295 }; 296 297 int board_qspi_init(void) 298 { 299 /* Set the iomux */ 300 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 301 ARRAY_SIZE(quadspi_pads)); 302 /* Set the clock */ 303 enable_qspi_clk(0); 304 305 return 0; 306 } 307 #endif 308 309 #ifdef CONFIG_FSL_ESDHC 310 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 311 {USDHC1_BASE_ADDR, 0, 4}, 312 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 313 {USDHC2_BASE_ADDR, 0, 8}, 314 #else 315 {USDHC2_BASE_ADDR, 0, 4}, 316 #endif 317 }; 318 319 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 320 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) 321 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) 322 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 323 324 int board_mmc_getcd(struct mmc *mmc) 325 { 326 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 327 int ret = 0; 328 329 switch (cfg->esdhc_base) { 330 case USDHC1_BASE_ADDR: 331 ret = !gpio_get_value(USDHC1_CD_GPIO); 332 break; 333 case USDHC2_BASE_ADDR: 334 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 335 ret = 1; 336 #else 337 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, 338 ARRAY_SIZE(usdhc2_cd_pads)); 339 gpio_direction_input(USDHC2_CD_GPIO); 340 341 /* 342 * Since it is the DAT3 pin, this pin is pulled to 343 * low voltage if no card 344 */ 345 ret = gpio_get_value(USDHC2_CD_GPIO); 346 347 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, 348 ARRAY_SIZE(usdhc2_dat3_pads)); 349 #endif 350 break; 351 } 352 353 return ret; 354 } 355 356 int board_mmc_init(bd_t *bis) 357 { 358 #ifdef CONFIG_SPL_BUILD 359 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 360 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, 361 ARRAY_SIZE(usdhc2_emmc_pads)); 362 #else 363 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 364 #endif 365 gpio_direction_output(USDHC2_PWR_GPIO, 0); 366 udelay(500); 367 gpio_direction_output(USDHC2_PWR_GPIO, 1); 368 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 369 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); 370 #else 371 int i, ret; 372 373 /* 374 * According to the board_mmc_init() the following map is done: 375 * (U-boot device node) (Physical Port) 376 * mmc0 USDHC1 377 * mmc1 USDHC2 378 */ 379 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 380 switch (i) { 381 case 0: 382 imx_iomux_v3_setup_multiple_pads( 383 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 384 gpio_direction_input(USDHC1_CD_GPIO); 385 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 386 387 gpio_direction_output(USDHC1_PWR_GPIO, 0); 388 udelay(500); 389 gpio_direction_output(USDHC1_PWR_GPIO, 1); 390 break; 391 case 1: 392 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 393 imx_iomux_v3_setup_multiple_pads( 394 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); 395 #else 396 imx_iomux_v3_setup_multiple_pads( 397 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 398 #endif 399 gpio_direction_output(USDHC2_PWR_GPIO, 0); 400 udelay(500); 401 gpio_direction_output(USDHC2_PWR_GPIO, 1); 402 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 403 break; 404 default: 405 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); 406 return -EINVAL; 407 } 408 409 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 410 if (ret) { 411 printf("Warning: failed to initialize mmc dev %d\n", i); 412 return ret; 413 } 414 } 415 #endif 416 return 0; 417 } 418 #endif 419 420 #ifdef CONFIG_USB_EHCI_MX6 421 #define USB_OTHERREGS_OFFSET 0x800 422 #define UCTRL_PWR_POL (1 << 9) 423 424 static iomux_v3_cfg_t const usb_otg_pads[] = { 425 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 426 }; 427 428 /* At default the 3v3 enables the MIC2026 for VBUS power */ 429 static void setup_usb(void) 430 { 431 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 432 ARRAY_SIZE(usb_otg_pads)); 433 } 434 435 int board_usb_phy_mode(int port) 436 { 437 if (port == 1) 438 return USB_INIT_HOST; 439 else 440 return usb_phy_mode(port); 441 } 442 443 int board_ehci_hcd_init(int port) 444 { 445 u32 *usbnc_usb_ctrl; 446 447 if (port > 1) 448 return -EINVAL; 449 450 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 451 port * 4); 452 453 /* Set Power polarity */ 454 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 455 456 return 0; 457 } 458 #endif 459 460 int board_early_init_f(void) 461 { 462 setup_iomux_uart(); 463 464 return 0; 465 } 466 467 int board_init(void) 468 { 469 /* Address of boot parameters */ 470 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 471 472 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 473 474 iox74lv_init(); 475 476 #ifdef CONFIG_SYS_I2C_MXC 477 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 478 #endif 479 480 #ifdef CONFIG_USB_EHCI_MX6 481 setup_usb(); 482 #endif 483 484 #ifdef CONFIG_FSL_QSPI 485 board_qspi_init(); 486 #endif 487 488 return 0; 489 } 490 491 #ifdef CONFIG_CMD_BMODE 492 static const struct boot_mode board_boot_modes[] = { 493 /* 4 bit bus width */ 494 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, 495 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 496 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 497 {NULL, 0}, 498 }; 499 #endif 500 501 int board_late_init(void) 502 { 503 #ifdef CONFIG_CMD_BMODE 504 add_board_boot_modes(board_boot_modes); 505 #endif 506 507 return 0; 508 } 509 510 u32 get_board_rev(void) 511 { 512 return get_cpu_rev(); 513 } 514 515 int checkboard(void) 516 { 517 puts("Board: MX6UL 14x14 EVK\n"); 518 519 return 0; 520 } 521 522 #ifdef CONFIG_SPL_BUILD 523 #include <libfdt.h> 524 #include <spl.h> 525 #include <asm/arch/mx6-ddr.h> 526 527 const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 528 .dram_dqm0 = 0x00000030, 529 .dram_dqm1 = 0x00000030, 530 .dram_ras = 0x00000030, 531 .dram_cas = 0x00000030, 532 .dram_odt0 = 0x00000030, 533 .dram_odt1 = 0x00000030, 534 .dram_sdba2 = 0x00000000, 535 .dram_sdclk_0 = 0x00000008, 536 .dram_sdqs0 = 0x00000038, 537 .dram_sdqs1 = 0x00000030, 538 .dram_reset = 0x00000030, 539 }; 540 541 const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 542 .grp_addds = 0x00000030, 543 .grp_ddrmode_ctl = 0x00020000, 544 .grp_b0ds = 0x00000030, 545 .grp_ctlds = 0x00000030, 546 .grp_b1ds = 0x00000030, 547 .grp_ddrpke = 0x00000000, 548 .grp_ddrmode = 0x00020000, 549 .grp_ddr_type = 0x000c0000, 550 }; 551 552 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 553 .p0_mpwldectrl0 = 0x00070007, 554 .p0_mpdgctrl0 = 0x41490145, 555 .p0_mprddlctl = 0x40404546, 556 .p0_mpwrdlctl = 0x4040524D, 557 }; 558 559 static struct mx6_ddr3_cfg mem_ddr = { 560 .mem_speed = 800, 561 .density = 4, 562 .width = 16, 563 .banks = 8, 564 .rowaddr = 15, 565 .coladdr = 10, 566 .pagesz = 2, 567 .trcd = 1375, 568 .trcmin = 4875, 569 .trasmin = 3500, 570 }; 571 572 static void ccgr_init(void) 573 { 574 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 575 576 writel(0xFFFFFFFF, &ccm->CCGR0); 577 writel(0xFFFFFFFF, &ccm->CCGR1); 578 writel(0xFFFFFFFF, &ccm->CCGR2); 579 writel(0xFFFFFFFF, &ccm->CCGR3); 580 writel(0xFFFFFFFF, &ccm->CCGR4); 581 writel(0xFFFFFFFF, &ccm->CCGR5); 582 writel(0xFFFFFFFF, &ccm->CCGR6); 583 writel(0xFFFFFFFF, &ccm->CCGR7); 584 } 585 586 static void spl_dram_init(void) 587 { 588 struct mx6_ddr_sysinfo sysinfo = { 589 .dsize = 0, 590 .cs_density = 20, 591 .ncs = 1, 592 .cs1_mirror = 0, 593 .rtt_wr = 2, 594 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 595 .walat = 1, /* Write additional latency */ 596 .ralat = 5, /* Read additional latency */ 597 .mif3_mode = 3, /* Command prediction working mode */ 598 .bi_on = 1, /* Bank interleaving enabled */ 599 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 600 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 601 }; 602 603 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 604 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 605 } 606 607 void board_init_f(ulong dummy) 608 { 609 /* setup AIPS and disable watchdog */ 610 arch_cpu_init(); 611 612 ccgr_init(); 613 614 /* iomux and setup of i2c */ 615 board_early_init_f(); 616 617 /* setup GP timer */ 618 timer_init(); 619 620 /* UART clocks enabled and gd valid - init serial console */ 621 preloader_console_init(); 622 623 /* DDR initialization */ 624 spl_dram_init(); 625 626 /* Clear the BSS. */ 627 memset(__bss_start, 0, __bss_end - __bss_start); 628 629 /* load/boot image from boot device */ 630 board_init_r(NULL, 0); 631 } 632 633 void reset_cpu(ulong addr) 634 { 635 } 636 #endif 637