1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/iomux.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/mx6ul_pins.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/boot_mode.h> 17 #include <asm/imx-common/mxc_i2c.h> 18 #include <asm/io.h> 19 #include <common.h> 20 #include <fsl_esdhc.h> 21 #include <i2c.h> 22 #include <miiphy.h> 23 #include <linux/sizes.h> 24 #include <mmc.h> 25 #include <netdev.h> 26 #include <power/pmic.h> 27 #include <power/pfuze3000_pmic.h> 28 #include "../common/pfuze.h" 29 #include <usb.h> 30 #include <usb/ehci-ci.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 37 38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 42 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 45 46 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 49 PAD_CTL_ODE) 50 51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 52 PAD_CTL_SPEED_HIGH | \ 53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 54 55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 57 58 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 59 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 60 61 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 62 63 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 64 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 65 66 #define IOX_SDI IMX_GPIO_NR(5, 10) 67 #define IOX_STCP IMX_GPIO_NR(5, 7) 68 #define IOX_SHCP IMX_GPIO_NR(5, 11) 69 #define IOX_OE IMX_GPIO_NR(5, 8) 70 71 static iomux_v3_cfg_t const iox_pads[] = { 72 /* IOX_SDI */ 73 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 74 /* IOX_SHCP */ 75 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 76 /* IOX_STCP */ 77 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 78 /* IOX_nOE */ 79 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 80 }; 81 82 /* 83 * HDMI_nRST --> Q0 84 * ENET1_nRST --> Q1 85 * ENET2_nRST --> Q2 86 * CAN1_2_STBY --> Q3 87 * BT_nPWD --> Q4 88 * CSI_RST --> Q5 89 * CSI_PWDN --> Q6 90 * LCD_nPWREN --> Q7 91 */ 92 enum qn { 93 HDMI_NRST, 94 ENET1_NRST, 95 ENET2_NRST, 96 CAN1_2_STBY, 97 BT_NPWD, 98 CSI_RST, 99 CSI_PWDN, 100 LCD_NPWREN, 101 }; 102 103 enum qn_func { 104 qn_reset, 105 qn_enable, 106 qn_disable, 107 }; 108 109 enum qn_level { 110 qn_low = 0, 111 qn_high = 1, 112 }; 113 114 static enum qn_level seq[3][2] = { 115 {0, 1}, {1, 1}, {0, 0} 116 }; 117 118 static enum qn_func qn_output[8] = { 119 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, 120 qn_disable, qn_disable 121 }; 122 123 static void iox74lv_init(void) 124 { 125 int i; 126 127 gpio_direction_output(IOX_OE, 0); 128 129 for (i = 7; i >= 0; i--) { 130 gpio_direction_output(IOX_SHCP, 0); 131 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 132 udelay(500); 133 gpio_direction_output(IOX_SHCP, 1); 134 udelay(500); 135 } 136 137 gpio_direction_output(IOX_STCP, 0); 138 udelay(500); 139 /* 140 * shift register will be output to pins 141 */ 142 gpio_direction_output(IOX_STCP, 1); 143 144 for (i = 7; i >= 0; i--) { 145 gpio_direction_output(IOX_SHCP, 0); 146 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 147 udelay(500); 148 gpio_direction_output(IOX_SHCP, 1); 149 udelay(500); 150 } 151 gpio_direction_output(IOX_STCP, 0); 152 udelay(500); 153 /* 154 * shift register will be output to pins 155 */ 156 gpio_direction_output(IOX_STCP, 1); 157 }; 158 159 #ifdef CONFIG_SYS_I2C_MXC 160 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 161 /* I2C1 for PMIC and EEPROM */ 162 static struct i2c_pads_info i2c_pad_info1 = { 163 .scl = { 164 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, 165 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, 166 .gp = IMX_GPIO_NR(1, 28), 167 }, 168 .sda = { 169 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, 170 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, 171 .gp = IMX_GPIO_NR(1, 29), 172 }, 173 }; 174 175 #ifdef CONFIG_POWER 176 #define I2C_PMIC 0 177 int power_init_board(void) 178 { 179 if (is_mx6ul_9x9_evk()) { 180 struct pmic *pfuze; 181 int ret; 182 unsigned int reg, rev_id; 183 184 ret = power_pfuze3000_init(I2C_PMIC); 185 if (ret) 186 return ret; 187 188 pfuze = pmic_get("PFUZE3000"); 189 ret = pmic_probe(pfuze); 190 if (ret) 191 return ret; 192 193 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); 194 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); 195 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", 196 reg, rev_id); 197 198 /* disable Low Power Mode during standby mode */ 199 pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); 200 reg |= 0x1; 201 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); 202 203 /* SW1B step ramp up time from 2us to 4us/25mV */ 204 reg = 0x40; 205 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); 206 207 /* SW1B mode to APS/PFM */ 208 reg = 0xc; 209 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); 210 211 /* SW1B standby voltage set to 0.975V */ 212 reg = 0xb; 213 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); 214 } 215 216 return 0; 217 } 218 #endif 219 #endif 220 221 int dram_init(void) 222 { 223 gd->ram_size = imx_ddr_size(); 224 225 return 0; 226 } 227 228 static iomux_v3_cfg_t const uart1_pads[] = { 229 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 230 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 231 }; 232 233 static iomux_v3_cfg_t const usdhc1_pads[] = { 234 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 235 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 236 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 237 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 238 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 239 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 240 241 /* VSELECT */ 242 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 243 /* CD */ 244 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 245 /* RST_B */ 246 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 247 }; 248 249 /* 250 * mx6ul_14x14_evk board default supports sd card. If want to use 251 * EMMC, need to do board rework for sd2. 252 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support 253 * emmc, need to define this macro. 254 */ 255 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 256 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { 257 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 258 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 259 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 260 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 261 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 262 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 263 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 264 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 265 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 266 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 267 268 /* 269 * RST_B 270 */ 271 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 272 }; 273 #else 274 static iomux_v3_cfg_t const usdhc2_pads[] = { 275 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 276 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 277 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 278 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 279 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 280 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 281 }; 282 283 static iomux_v3_cfg_t const usdhc2_cd_pads[] = { 284 /* 285 * The evk board uses DAT3 to detect CD card plugin, 286 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. 287 */ 288 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 289 }; 290 291 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { 292 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | 293 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 294 }; 295 #endif 296 297 static void setup_iomux_uart(void) 298 { 299 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 300 } 301 302 #ifdef CONFIG_FSL_QSPI 303 304 #define QSPI_PAD_CTRL1 \ 305 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ 306 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) 307 308 static iomux_v3_cfg_t const quadspi_pads[] = { 309 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 310 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 311 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 312 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 313 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 314 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 315 }; 316 317 static int board_qspi_init(void) 318 { 319 /* Set the iomux */ 320 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 321 ARRAY_SIZE(quadspi_pads)); 322 /* Set the clock */ 323 enable_qspi_clk(0); 324 325 return 0; 326 } 327 #endif 328 329 #ifdef CONFIG_FSL_ESDHC 330 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 331 {USDHC1_BASE_ADDR, 0, 4}, 332 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 333 {USDHC2_BASE_ADDR, 0, 8}, 334 #else 335 {USDHC2_BASE_ADDR, 0, 4}, 336 #endif 337 }; 338 339 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 340 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) 341 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) 342 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 343 344 int board_mmc_getcd(struct mmc *mmc) 345 { 346 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 347 int ret = 0; 348 349 switch (cfg->esdhc_base) { 350 case USDHC1_BASE_ADDR: 351 ret = !gpio_get_value(USDHC1_CD_GPIO); 352 break; 353 case USDHC2_BASE_ADDR: 354 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 355 ret = 1; 356 #else 357 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, 358 ARRAY_SIZE(usdhc2_cd_pads)); 359 gpio_direction_input(USDHC2_CD_GPIO); 360 361 /* 362 * Since it is the DAT3 pin, this pin is pulled to 363 * low voltage if no card 364 */ 365 ret = gpio_get_value(USDHC2_CD_GPIO); 366 367 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, 368 ARRAY_SIZE(usdhc2_dat3_pads)); 369 #endif 370 break; 371 } 372 373 return ret; 374 } 375 376 int board_mmc_init(bd_t *bis) 377 { 378 #ifdef CONFIG_SPL_BUILD 379 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 380 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, 381 ARRAY_SIZE(usdhc2_emmc_pads)); 382 #else 383 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 384 #endif 385 gpio_direction_output(USDHC2_PWR_GPIO, 0); 386 udelay(500); 387 gpio_direction_output(USDHC2_PWR_GPIO, 1); 388 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 389 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); 390 #else 391 int i, ret; 392 393 /* 394 * According to the board_mmc_init() the following map is done: 395 * (U-Boot device node) (Physical Port) 396 * mmc0 USDHC1 397 * mmc1 USDHC2 398 */ 399 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 400 switch (i) { 401 case 0: 402 imx_iomux_v3_setup_multiple_pads( 403 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 404 gpio_direction_input(USDHC1_CD_GPIO); 405 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 406 407 gpio_direction_output(USDHC1_PWR_GPIO, 0); 408 udelay(500); 409 gpio_direction_output(USDHC1_PWR_GPIO, 1); 410 break; 411 case 1: 412 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 413 imx_iomux_v3_setup_multiple_pads( 414 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); 415 #else 416 imx_iomux_v3_setup_multiple_pads( 417 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 418 #endif 419 gpio_direction_output(USDHC2_PWR_GPIO, 0); 420 udelay(500); 421 gpio_direction_output(USDHC2_PWR_GPIO, 1); 422 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 423 break; 424 default: 425 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); 426 return -EINVAL; 427 } 428 429 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 430 if (ret) { 431 printf("Warning: failed to initialize mmc dev %d\n", i); 432 return ret; 433 } 434 } 435 #endif 436 return 0; 437 } 438 #endif 439 440 #ifdef CONFIG_USB_EHCI_MX6 441 #define USB_OTHERREGS_OFFSET 0x800 442 #define UCTRL_PWR_POL (1 << 9) 443 444 static iomux_v3_cfg_t const usb_otg_pads[] = { 445 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 446 }; 447 448 /* At default the 3v3 enables the MIC2026 for VBUS power */ 449 static void setup_usb(void) 450 { 451 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 452 ARRAY_SIZE(usb_otg_pads)); 453 } 454 455 int board_usb_phy_mode(int port) 456 { 457 if (port == 1) 458 return USB_INIT_HOST; 459 else 460 return usb_phy_mode(port); 461 } 462 463 int board_ehci_hcd_init(int port) 464 { 465 u32 *usbnc_usb_ctrl; 466 467 if (port > 1) 468 return -EINVAL; 469 470 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 471 port * 4); 472 473 /* Set Power polarity */ 474 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 475 476 return 0; 477 } 478 #endif 479 480 #ifdef CONFIG_FEC_MXC 481 /* 482 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only 483 * be used for ENET1 or ENET2, cannot be used for both. 484 */ 485 static iomux_v3_cfg_t const fec1_pads[] = { 486 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 487 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 488 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 489 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 490 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 491 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 492 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 493 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 494 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 495 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 496 }; 497 498 static iomux_v3_cfg_t const fec2_pads[] = { 499 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 500 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 501 502 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 503 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 504 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 505 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 506 507 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 508 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 509 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 510 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 511 }; 512 513 static void setup_iomux_fec(int fec_id) 514 { 515 if (fec_id == 0) 516 imx_iomux_v3_setup_multiple_pads(fec1_pads, 517 ARRAY_SIZE(fec1_pads)); 518 else 519 imx_iomux_v3_setup_multiple_pads(fec2_pads, 520 ARRAY_SIZE(fec2_pads)); 521 } 522 523 int board_eth_init(bd_t *bis) 524 { 525 setup_iomux_fec(CONFIG_FEC_ENET_DEV); 526 527 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 528 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 529 } 530 531 static int setup_fec(int fec_id) 532 { 533 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 534 int ret; 535 536 if (fec_id == 0) { 537 /* 538 * Use 50M anatop loopback REF_CLK1 for ENET1, 539 * clear gpr1[13], set gpr1[17]. 540 */ 541 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 542 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 543 } else { 544 /* 545 * Use 50M anatop loopback REF_CLK2 for ENET2, 546 * clear gpr1[14], set gpr1[18]. 547 */ 548 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 549 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 550 } 551 552 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 553 if (ret) 554 return ret; 555 556 enable_enet_clk(1); 557 558 return 0; 559 } 560 561 int board_phy_config(struct phy_device *phydev) 562 { 563 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 564 565 if (phydev->drv->config) 566 phydev->drv->config(phydev); 567 568 return 0; 569 } 570 #endif 571 572 #ifdef CONFIG_VIDEO_MXS 573 static iomux_v3_cfg_t const lcd_pads[] = { 574 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 575 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 576 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 577 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 578 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), 579 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), 580 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), 581 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), 582 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), 583 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), 584 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), 585 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), 586 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), 587 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), 588 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 589 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 590 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 591 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 592 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 593 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 594 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 595 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 596 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 597 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 598 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 599 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 600 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 601 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 602 603 /* LCD_RST */ 604 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 605 606 /* Use GPIO for Brightness adjustment, duty cycle = period. */ 607 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 608 }; 609 610 static int setup_lcd(void) 611 { 612 enable_lcdif_clock(LCDIF1_BASE_ADDR); 613 614 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 615 616 /* Reset the LCD */ 617 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); 618 udelay(500); 619 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); 620 621 /* Set Brightness to high */ 622 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); 623 624 return 0; 625 } 626 #endif 627 628 int board_early_init_f(void) 629 { 630 setup_iomux_uart(); 631 632 return 0; 633 } 634 635 int board_init(void) 636 { 637 /* Address of boot parameters */ 638 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 639 640 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 641 642 iox74lv_init(); 643 644 #ifdef CONFIG_SYS_I2C_MXC 645 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 646 #endif 647 648 #ifdef CONFIG_FEC_MXC 649 setup_fec(CONFIG_FEC_ENET_DEV); 650 #endif 651 652 #ifdef CONFIG_USB_EHCI_MX6 653 setup_usb(); 654 #endif 655 656 #ifdef CONFIG_FSL_QSPI 657 board_qspi_init(); 658 #endif 659 660 #ifdef CONFIG_VIDEO_MXS 661 setup_lcd(); 662 #endif 663 664 return 0; 665 } 666 667 #ifdef CONFIG_CMD_BMODE 668 static const struct boot_mode board_boot_modes[] = { 669 /* 4 bit bus width */ 670 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, 671 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 672 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 673 {NULL, 0}, 674 }; 675 #endif 676 677 int board_late_init(void) 678 { 679 #ifdef CONFIG_CMD_BMODE 680 add_board_boot_modes(board_boot_modes); 681 #endif 682 683 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 684 setenv("board_name", "EVK"); 685 686 if (is_mx6ul_9x9_evk()) 687 setenv("board_rev", "9X9"); 688 else 689 setenv("board_rev", "14X14"); 690 #endif 691 692 return 0; 693 } 694 695 int checkboard(void) 696 { 697 if (is_mx6ul_9x9_evk()) 698 puts("Board: MX6UL 9x9 EVK\n"); 699 else 700 puts("Board: MX6UL 14x14 EVK\n"); 701 702 return 0; 703 } 704 705 #ifdef CONFIG_SPL_BUILD 706 #include <libfdt.h> 707 #include <spl.h> 708 #include <asm/arch/mx6-ddr.h> 709 710 711 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 712 .grp_addds = 0x00000030, 713 .grp_ddrmode_ctl = 0x00020000, 714 .grp_b0ds = 0x00000030, 715 .grp_ctlds = 0x00000030, 716 .grp_b1ds = 0x00000030, 717 .grp_ddrpke = 0x00000000, 718 .grp_ddrmode = 0x00020000, 719 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 720 .grp_ddr_type = 0x00080000, 721 #else 722 .grp_ddr_type = 0x000c0000, 723 #endif 724 }; 725 726 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 727 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 728 .dram_dqm0 = 0x00000030, 729 .dram_dqm1 = 0x00000030, 730 .dram_ras = 0x00000030, 731 .dram_cas = 0x00000030, 732 .dram_odt0 = 0x00000000, 733 .dram_odt1 = 0x00000000, 734 .dram_sdba2 = 0x00000000, 735 .dram_sdclk_0 = 0x00000030, 736 .dram_sdqs0 = 0x00003030, 737 .dram_sdqs1 = 0x00003030, 738 .dram_reset = 0x00000030, 739 }; 740 741 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 742 .p0_mpwldectrl0 = 0x00000000, 743 .p0_mpdgctrl0 = 0x20000000, 744 .p0_mprddlctl = 0x4040484f, 745 .p0_mpwrdlctl = 0x40405247, 746 .mpzqlp2ctl = 0x1b4700c7, 747 }; 748 749 static struct mx6_lpddr2_cfg mem_ddr = { 750 .mem_speed = 800, 751 .density = 2, 752 .width = 16, 753 .banks = 4, 754 .rowaddr = 14, 755 .coladdr = 10, 756 .trcd_lp = 1500, 757 .trppb_lp = 1500, 758 .trpab_lp = 2000, 759 .trasmin = 4250, 760 }; 761 762 struct mx6_ddr_sysinfo ddr_sysinfo = { 763 .dsize = 0, 764 .cs_density = 18, 765 .ncs = 1, 766 .cs1_mirror = 0, 767 .walat = 0, 768 .ralat = 5, 769 .mif3_mode = 3, 770 .bi_on = 1, 771 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ 772 .rtt_nom = 0, 773 .sde_to_rst = 0, /* LPDDR2 does not need this field */ 774 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ 775 .ddr_type = DDR_TYPE_LPDDR2, 776 }; 777 778 #else 779 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 780 .dram_dqm0 = 0x00000030, 781 .dram_dqm1 = 0x00000030, 782 .dram_ras = 0x00000030, 783 .dram_cas = 0x00000030, 784 .dram_odt0 = 0x00000030, 785 .dram_odt1 = 0x00000030, 786 .dram_sdba2 = 0x00000000, 787 .dram_sdclk_0 = 0x00000008, 788 .dram_sdqs0 = 0x00000038, 789 .dram_sdqs1 = 0x00000030, 790 .dram_reset = 0x00000030, 791 }; 792 793 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 794 .p0_mpwldectrl0 = 0x00070007, 795 .p0_mpdgctrl0 = 0x41490145, 796 .p0_mprddlctl = 0x40404546, 797 .p0_mpwrdlctl = 0x4040524D, 798 }; 799 800 struct mx6_ddr_sysinfo ddr_sysinfo = { 801 .dsize = 0, 802 .cs_density = 20, 803 .ncs = 1, 804 .cs1_mirror = 0, 805 .rtt_wr = 2, 806 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 807 .walat = 1, /* Write additional latency */ 808 .ralat = 5, /* Read additional latency */ 809 .mif3_mode = 3, /* Command prediction working mode */ 810 .bi_on = 1, /* Bank interleaving enabled */ 811 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 812 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 813 .ddr_type = DDR_TYPE_DDR3, 814 }; 815 816 static struct mx6_ddr3_cfg mem_ddr = { 817 .mem_speed = 800, 818 .density = 4, 819 .width = 16, 820 .banks = 8, 821 .rowaddr = 15, 822 .coladdr = 10, 823 .pagesz = 2, 824 .trcd = 1375, 825 .trcmin = 4875, 826 .trasmin = 3500, 827 }; 828 #endif 829 830 static void ccgr_init(void) 831 { 832 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 833 834 writel(0xFFFFFFFF, &ccm->CCGR0); 835 writel(0xFFFFFFFF, &ccm->CCGR1); 836 writel(0xFFFFFFFF, &ccm->CCGR2); 837 writel(0xFFFFFFFF, &ccm->CCGR3); 838 writel(0xFFFFFFFF, &ccm->CCGR4); 839 writel(0xFFFFFFFF, &ccm->CCGR5); 840 writel(0xFFFFFFFF, &ccm->CCGR6); 841 writel(0xFFFFFFFF, &ccm->CCGR7); 842 } 843 844 static void spl_dram_init(void) 845 { 846 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 847 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 848 } 849 850 void board_init_f(ulong dummy) 851 { 852 /* setup AIPS and disable watchdog */ 853 arch_cpu_init(); 854 855 ccgr_init(); 856 857 /* iomux and setup of i2c */ 858 board_early_init_f(); 859 860 /* setup GP timer */ 861 timer_init(); 862 863 /* UART clocks enabled and gd valid - init serial console */ 864 preloader_console_init(); 865 866 /* DDR initialization */ 867 spl_dram_init(); 868 869 /* Clear the BSS. */ 870 memset(__bss_start, 0, __bss_end - __bss_start); 871 872 /* load/boot image from boot device */ 873 board_init_r(NULL, 0); 874 } 875 #endif 876