1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/gpio.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/io.h> 18 #include <asm/imx-common/mxc_i2c.h> 19 #include <linux/sizes.h> 20 #include <common.h> 21 #include <fsl_esdhc.h> 22 #include <mmc.h> 23 #include <i2c.h> 24 #include <miiphy.h> 25 #include <netdev.h> 26 #include <power/pmic.h> 27 #include <power/pfuze100_pmic.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 40 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 41 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 42 PAD_CTL_ODE) 43 44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 45 PAD_CTL_SPEED_HIGH | \ 46 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 47 48 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ 49 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) 50 51 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 52 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 53 54 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 56 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 57 PAD_CTL_ODE) 58 59 int dram_init(void) 60 { 61 gd->ram_size = PHYS_SDRAM_SIZE; 62 63 return 0; 64 } 65 66 static iomux_v3_cfg_t const uart1_pads[] = { 67 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 68 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 69 }; 70 71 static iomux_v3_cfg_t const usdhc4_pads[] = { 72 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 79 }; 80 81 static iomux_v3_cfg_t const fec1_pads[] = { 82 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 85 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 86 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 87 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 88 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 89 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 90 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 91 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 92 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 93 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 94 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 95 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 96 }; 97 98 static iomux_v3_cfg_t const peri_3v3_pads[] = { 99 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 100 }; 101 102 static iomux_v3_cfg_t const phy_control_pads[] = { 103 /* 25MHz Ethernet PHY Clock */ 104 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 105 106 /* ENET PHY Power */ 107 MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), 108 109 /* AR8031 PHY Reset */ 110 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 111 }; 112 113 static void setup_iomux_uart(void) 114 { 115 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 116 } 117 118 static int setup_fec(void) 119 { 120 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 121 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 122 int ret; 123 int reg; 124 125 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ 126 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); 127 128 imx_iomux_v3_setup_multiple_pads(phy_control_pads, 129 ARRAY_SIZE(phy_control_pads)); 130 131 /* Enable the ENET power, active low */ 132 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); 133 134 /* Reset AR8031 PHY */ 135 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); 136 udelay(500); 137 gpio_set_value(IMX_GPIO_NR(2, 7), 1); 138 139 reg = readl(&anatop->pll_enet); 140 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; 141 writel(reg, &anatop->pll_enet); 142 143 ret = enable_fec_anatop_clock(ENET_125MHz); 144 if (ret) 145 return ret; 146 147 return 0; 148 } 149 150 int board_eth_init(bd_t *bis) 151 { 152 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 153 setup_fec(); 154 155 return cpu_eth_init(bis); 156 } 157 158 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 159 /* I2C1 for PMIC */ 160 static struct i2c_pads_info i2c_pad_info1 = { 161 .scl = { 162 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, 163 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, 164 .gp = IMX_GPIO_NR(1, 0), 165 }, 166 .sda = { 167 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, 168 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, 169 .gp = IMX_GPIO_NR(1, 1), 170 }, 171 }; 172 173 static int pfuze_init(void) 174 { 175 struct pmic *p; 176 int ret; 177 unsigned int reg; 178 179 ret = power_pfuze100_init(I2C_PMIC); 180 if (ret) 181 return ret; 182 183 p = pmic_get("PFUZE100"); 184 ret = pmic_probe(p); 185 if (ret) 186 return ret; 187 188 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 189 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 190 191 /* Set SW1AB standby voltage to 0.975V */ 192 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); 193 reg &= ~0x3f; 194 reg |= 0x1b; 195 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); 196 197 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 198 pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); 199 reg &= ~0xc0; 200 reg |= 0x40; 201 pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); 202 203 /* Set SW1C standby voltage to 0.975V */ 204 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); 205 reg &= ~0x3f; 206 reg |= 0x1b; 207 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); 208 209 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ 210 pmic_reg_read(p, PFUZE100_SW1CCONF, ®); 211 reg &= ~0xc0; 212 reg |= 0x40; 213 pmic_reg_write(p, PFUZE100_SW1CCONF, reg); 214 215 /* Enable power of VGEN5 3V3, needed for SD3 */ 216 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 217 reg &= ~0x1F; 218 reg |= 0x1F; 219 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 220 221 return 0; 222 } 223 224 int board_phy_config(struct phy_device *phydev) 225 { 226 /* 227 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on 228 * Phy control debug reg 0 229 */ 230 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 231 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 232 233 /* rgmii tx clock delay enable */ 234 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 235 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 236 237 if (phydev->drv->config) 238 phydev->drv->config(phydev); 239 240 return 0; 241 } 242 243 int board_early_init_f(void) 244 { 245 setup_iomux_uart(); 246 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 247 248 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 249 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, 250 ARRAY_SIZE(peri_3v3_pads)); 251 252 /* Active high for ncp692 */ 253 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); 254 255 return 0; 256 } 257 258 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 259 {USDHC4_BASE_ADDR}, 260 }; 261 262 int board_mmc_getcd(struct mmc *mmc) 263 { 264 return 1; /* Assume boot SD always present */ 265 } 266 267 int board_mmc_init(bd_t *bis) 268 { 269 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 270 271 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 272 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 273 } 274 275 int board_init(void) 276 { 277 /* Address of boot parameters */ 278 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 279 280 return 0; 281 } 282 283 int board_late_init(void) 284 { 285 pfuze_init(); 286 287 return 0; 288 } 289 290 int checkboard(void) 291 { 292 puts("Board: MX6SX SABRE SDB\n"); 293 294 return 0; 295 } 296