1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014 Freescale Semiconductor, Inc.
4  *
5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
6  */
7 
8 #include <asm/arch/clock.h>
9 #include <asm/arch/crm_regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/io.h>
17 #include <asm/mach-imx/mxc_i2c.h>
18 #include <linux/sizes.h>
19 #include <common.h>
20 #include <fsl_esdhc.h>
21 #include <mmc.h>
22 #include <i2c.h>
23 #include <miiphy.h>
24 #include <netdev.h>
25 #include <power/pmic.h>
26 #include <power/pfuze100_pmic.h>
27 #include "../common/pfuze.h"
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
32 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
33 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
34 
35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
36 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
37 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
38 
39 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
40 	PAD_CTL_SPEED_HIGH   |                                   \
41 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
42 
43 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
44 	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
45 
46 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
47 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
48 
49 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
50 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
51 
52 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
53 	PAD_CTL_DSE_40ohm)
54 
55 int dram_init(void)
56 {
57 	gd->ram_size = imx_ddr_size();
58 
59 	return 0;
60 }
61 
62 static iomux_v3_cfg_t const uart1_pads[] = {
63 	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 };
66 
67 static iomux_v3_cfg_t const wdog_b_pad = {
68 	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
69 };
70 static iomux_v3_cfg_t const fec1_pads[] = {
71 	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
74 	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
75 	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
76 	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
77 	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
78 	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
79 	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 };
86 
87 static iomux_v3_cfg_t const peri_3v3_pads[] = {
88 	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
89 };
90 
91 static iomux_v3_cfg_t const phy_control_pads[] = {
92 	/* 25MHz Ethernet PHY Clock */
93 	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
94 
95 	/* ENET PHY Power */
96 	MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
97 
98 	/* AR8031 PHY Reset */
99 	MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
100 };
101 
102 static void setup_iomux_uart(void)
103 {
104 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
105 }
106 
107 static int setup_fec(void)
108 {
109 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
110 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
111 	int reg, ret;
112 
113 	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
114 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
115 
116 	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
117 	if (ret)
118 		return ret;
119 
120 	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
121 					 ARRAY_SIZE(phy_control_pads));
122 
123 	/* Enable the ENET power, active low */
124 	gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
125 	gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
126 
127 	/* Reset AR8031 PHY */
128 	gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
129 	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
130 	mdelay(10);
131 	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
132 
133 	reg = readl(&anatop->pll_enet);
134 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
135 	writel(reg, &anatop->pll_enet);
136 
137 	return 0;
138 }
139 
140 int board_eth_init(bd_t *bis)
141 {
142 	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
143 	setup_fec();
144 
145 	return cpu_eth_init(bis);
146 }
147 
148 int power_init_board(void)
149 {
150 	struct udevice *dev;
151 	unsigned int reg;
152 	int ret;
153 
154 	dev = pfuze_common_init();
155 	if (!dev)
156 		return -ENODEV;
157 
158 	ret = pfuze_mode_init(dev, APS_PFM);
159 	if (ret < 0)
160 		return ret;
161 
162 	/* Enable power of VGEN5 3V3, needed for SD3 */
163 	reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
164 	reg &= ~LDO_VOL_MASK;
165 	reg |= (LDOB_3_30V | (1 << LDO_EN));
166 	pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
167 
168 	return 0;
169 }
170 
171 int board_phy_config(struct phy_device *phydev)
172 {
173 	/*
174 	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
175 	 * Phy control debug reg 0
176 	 */
177 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
178 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
179 
180 	/* rgmii tx clock delay enable */
181 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
182 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
183 
184 	if (phydev->drv->config)
185 		phydev->drv->config(phydev);
186 
187 	return 0;
188 }
189 
190 int board_early_init_f(void)
191 {
192 	setup_iomux_uart();
193 
194 	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
195 	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
196 					 ARRAY_SIZE(peri_3v3_pads));
197 
198 	return 0;
199 }
200 
201 int board_mmc_get_env_dev(int devno)
202 {
203 	return devno;
204 }
205 
206 #ifdef CONFIG_FSL_QSPI
207 
208 int board_qspi_init(void)
209 {
210 	/* Set the clock */
211 	enable_qspi_clk(1);
212 
213 	return 0;
214 }
215 #endif
216 
217 #ifdef CONFIG_VIDEO_MXS
218 static iomux_v3_cfg_t const lcd_pads[] = {
219 	MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
220 	MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
221 	MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
222 	MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
223 	MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
224 	MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
225 	MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
226 	MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
227 	MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
228 	MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
229 	MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
230 	MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
231 	MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
232 	MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
233 	MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
234 	MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
235 	MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
236 	MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
237 	MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
238 	MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
239 	MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
240 	MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
241 	MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
242 	MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
243 	MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
244 	MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
245 	MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
246 	MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
247 	MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
248 
249 	/* Use GPIO for Brightness adjustment, duty cycle = period */
250 	MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
251 };
252 
253 static int setup_lcd(void)
254 {
255 	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
256 
257 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
258 
259 	/* Reset the LCD */
260 	gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
261 	gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
262 	udelay(500);
263 	gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
264 
265 	/* Set Brightness to high */
266 	gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
267 	gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
268 
269 	return 0;
270 }
271 #endif
272 
273 int board_init(void)
274 {
275 	/* Address of boot parameters */
276 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
277 
278 	/*
279 	 * Because kernel set WDOG_B mux before pad with the common pinctrl
280 	 * framwork now and wdog reset will be triggered once set WDOG_B mux
281 	 * with default pad setting, we set pad setting here to workaround this.
282 	 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
283 	 * as GPIO mux firstly here to workaround it.
284 	 */
285 	imx_iomux_v3_setup_pad(wdog_b_pad);
286 
287 	/* Active high for ncp692 */
288 	gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
289 	gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
290 
291 #ifdef CONFIG_FSL_QSPI
292 	board_qspi_init();
293 #endif
294 
295 #ifdef CONFIG_VIDEO_MXS
296 	setup_lcd();
297 #endif
298 
299 	return 0;
300 }
301 
302 static bool is_reva(void)
303 {
304 	return (nxp_board_rev() == 1);
305 }
306 
307 int board_late_init(void)
308 {
309 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
310 	if (is_reva())
311 		env_set("board_rev", "REVA");
312 #endif
313 	return 0;
314 }
315 
316 int checkboard(void)
317 {
318 	printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
319 
320 	return 0;
321 }
322 
323 #ifdef CONFIG_SPL_BUILD
324 #include <linux/libfdt.h>
325 #include <spl.h>
326 #include <asm/arch/mx6-ddr.h>
327 
328 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
329 	{USDHC2_BASE_ADDR, 0, 4},
330 	{USDHC3_BASE_ADDR},
331 	{USDHC4_BASE_ADDR},
332 };
333 
334 #define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 10)
335 #define USDHC3_PWR_GPIO	IMX_GPIO_NR(2, 11)
336 #define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 21)
337 
338 static iomux_v3_cfg_t const usdhc2_pads[] = {
339 	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
340 	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
341 	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
342 	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
343 	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
344 	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
345 };
346 
347 static iomux_v3_cfg_t const usdhc3_pads[] = {
348 	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
349 	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
350 	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
351 	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
352 	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
353 	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
354 	MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
355 	MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
356 	MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
357 	MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
358 
359 	/* CD pin */
360 	MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
361 
362 	/* RST_B, used for power reset cycle */
363 	MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
364 };
365 
366 static iomux_v3_cfg_t const usdhc4_pads[] = {
367 	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
368 	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
369 	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
370 	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
371 	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
372 	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
373 	MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
374 };
375 
376 int board_mmc_init(bd_t *bis)
377 {
378 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
379 	u32 val;
380 	u32 port;
381 
382 	val = readl(&src_regs->sbmr1);
383 
384 	if ((val & 0xc0) != 0x40) {
385 		printf("Not boot from USDHC!\n");
386 		return -EINVAL;
387 	}
388 
389 	port = (val >> 11) & 0x3;
390 	printf("port %d\n", port);
391 	switch (port) {
392 	case 1:
393 		imx_iomux_v3_setup_multiple_pads(
394 			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
395 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
396 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
397 		break;
398 	case 2:
399 		imx_iomux_v3_setup_multiple_pads(
400 			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
401 		gpio_direction_input(USDHC3_CD_GPIO);
402 		gpio_direction_output(USDHC3_PWR_GPIO, 1);
403 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
404 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
405 		break;
406 	case 3:
407 		imx_iomux_v3_setup_multiple_pads(
408 			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
409 		gpio_direction_input(USDHC4_CD_GPIO);
410 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
411 		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
412 		break;
413 	}
414 
415 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
416 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
417 }
418 
419 int board_mmc_getcd(struct mmc *mmc)
420 {
421 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
422 	int ret = 0;
423 
424 	switch (cfg->esdhc_base) {
425 	case USDHC2_BASE_ADDR:
426 		ret = 1; /* Assume uSDHC2 is always present */
427 		break;
428 	case USDHC3_BASE_ADDR:
429 		ret = !gpio_get_value(USDHC3_CD_GPIO);
430 		break;
431 	case USDHC4_BASE_ADDR:
432 		ret = !gpio_get_value(USDHC4_CD_GPIO);
433 		break;
434 	}
435 
436 	return ret;
437 }
438 
439 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
440 	.dram_dqm0 = 0x00000028,
441 	.dram_dqm1 = 0x00000028,
442 	.dram_dqm2 = 0x00000028,
443 	.dram_dqm3 = 0x00000028,
444 	.dram_ras = 0x00000020,
445 	.dram_cas = 0x00000020,
446 	.dram_odt0 = 0x00000020,
447 	.dram_odt1 = 0x00000020,
448 	.dram_sdba2 = 0x00000000,
449 	.dram_sdcke0 = 0x00003000,
450 	.dram_sdcke1 = 0x00003000,
451 	.dram_sdclk_0 = 0x00000030,
452 	.dram_sdqs0 = 0x00000028,
453 	.dram_sdqs1 = 0x00000028,
454 	.dram_sdqs2 = 0x00000028,
455 	.dram_sdqs3 = 0x00000028,
456 	.dram_reset = 0x00000020,
457 };
458 
459 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
460 	.grp_addds = 0x00000020,
461 	.grp_ddrmode_ctl = 0x00020000,
462 	.grp_ddrpke = 0x00000000,
463 	.grp_ddrmode = 0x00020000,
464 	.grp_b0ds = 0x00000028,
465 	.grp_b1ds = 0x00000028,
466 	.grp_ctlds = 0x00000020,
467 	.grp_ddr_type = 0x000c0000,
468 	.grp_b2ds = 0x00000028,
469 	.grp_b3ds = 0x00000028,
470 };
471 
472 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
473 	.p0_mpwldectrl0 = 0x00290025,
474 	.p0_mpwldectrl1 = 0x00220022,
475 	.p0_mpdgctrl0 = 0x41480144,
476 	.p0_mpdgctrl1 = 0x01340130,
477 	.p0_mprddlctl = 0x3C3E4244,
478 	.p0_mpwrdlctl = 0x34363638,
479 };
480 
481 static struct mx6_ddr3_cfg mem_ddr = {
482 	.mem_speed = 1600,
483 	.density = 4,
484 	.width = 32,
485 	.banks = 8,
486 	.rowaddr = 15,
487 	.coladdr = 10,
488 	.pagesz = 2,
489 	.trcd = 1375,
490 	.trcmin = 4875,
491 	.trasmin = 3500,
492 };
493 
494 static void ccgr_init(void)
495 {
496 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
497 
498 	writel(0xFFFFFFFF, &ccm->CCGR0);
499 	writel(0xFFFFFFFF, &ccm->CCGR1);
500 	writel(0xFFFFFFFF, &ccm->CCGR2);
501 	writel(0xFFFFFFFF, &ccm->CCGR3);
502 	writel(0xFFFFFFFF, &ccm->CCGR4);
503 	writel(0xFFFFFFFF, &ccm->CCGR5);
504 	writel(0xFFFFFFFF, &ccm->CCGR6);
505 	writel(0xFFFFFFFF, &ccm->CCGR7);
506 }
507 
508 static void spl_dram_init(void)
509 {
510 	struct mx6_ddr_sysinfo sysinfo = {
511 		.dsize = mem_ddr.width/32,
512 		.cs_density = 24,
513 		.ncs = 1,
514 		.cs1_mirror = 0,
515 		.rtt_wr = 2,
516 		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
517 		.walat = 1,		/* Write additional latency */
518 		.ralat = 5,		/* Read additional latency */
519 		.mif3_mode = 3,		/* Command prediction working mode */
520 		.bi_on = 1,		/* Bank interleaving enabled */
521 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
522 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
523 		.ddr_type = DDR_TYPE_DDR3,
524 		.refsel = 1,	/* Refresh cycles at 32KHz */
525 		.refr = 7,	/* 8 refresh commands per refresh cycle */
526 	};
527 
528 	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
529 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
530 }
531 
532 void board_init_f(ulong dummy)
533 {
534 	/* setup AIPS and disable watchdog */
535 	arch_cpu_init();
536 
537 	ccgr_init();
538 
539 	/* iomux and setup of i2c */
540 	board_early_init_f();
541 
542 	/* setup GP timer */
543 	timer_init();
544 
545 	/* UART clocks enabled and gd valid - init serial console */
546 	preloader_console_init();
547 
548 	/* DDR initialization */
549 	spl_dram_init();
550 
551 	/* Clear the BSS. */
552 	memset(__bss_start, 0, __bss_end - __bss_start);
553 
554 	/* load/boot image from boot device */
555 	board_init_r(NULL, 0);
556 }
557 #endif
558