1 /*
2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/io.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <linux/sizes.h>
20 #include <common.h>
21 #include <fsl_esdhc.h>
22 #include <mmc.h>
23 #include <i2c.h>
24 #include <miiphy.h>
25 #include <netdev.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
28 #include "../common/pfuze.h"
29 #include <usb.h>
30 #include <usb/ehci-fsl.h>
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
35 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
36 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
37 
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
39 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
40 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
41 
42 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
43 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
44 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
45 	PAD_CTL_ODE)
46 
47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
48 	PAD_CTL_SPEED_HIGH   |                                   \
49 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
50 
51 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
52 	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
53 
54 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
55 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
56 
57 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
58 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
59 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
60 	PAD_CTL_ODE)
61 
62 int dram_init(void)
63 {
64 	gd->ram_size = PHYS_SDRAM_SIZE;
65 
66 	return 0;
67 }
68 
69 static iomux_v3_cfg_t const uart1_pads[] = {
70 	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
71 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
72 };
73 
74 static iomux_v3_cfg_t const usdhc2_pads[] = {
75 	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 };
82 
83 static iomux_v3_cfg_t const usdhc3_pads[] = {
84 	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 	MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 	MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 	MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 	MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 
95 	/* CD pin */
96 	MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
97 
98 	/* RST_B, used for power reset cycle */
99 	MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
100 };
101 
102 static iomux_v3_cfg_t const usdhc4_pads[] = {
103 	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 	MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
110 };
111 
112 static iomux_v3_cfg_t const fec1_pads[] = {
113 	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
116 	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
117 	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
118 	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
119 	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
120 	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
121 	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
127 };
128 
129 static iomux_v3_cfg_t const peri_3v3_pads[] = {
130 	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
131 };
132 
133 static iomux_v3_cfg_t const phy_control_pads[] = {
134 	/* 25MHz Ethernet PHY Clock */
135 	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
136 
137 	/* ENET PHY Power */
138 	MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
139 
140 	/* AR8031 PHY Reset */
141 	MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
142 };
143 
144 static void setup_iomux_uart(void)
145 {
146 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
147 }
148 
149 static int setup_fec(void)
150 {
151 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
152 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
153 	int reg;
154 
155 	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
156 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
157 
158 	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
159 					 ARRAY_SIZE(phy_control_pads));
160 
161 	/* Enable the ENET power, active low */
162 	gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
163 
164 	/* Reset AR8031 PHY */
165 	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
166 	udelay(500);
167 	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
168 
169 	reg = readl(&anatop->pll_enet);
170 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
171 	writel(reg, &anatop->pll_enet);
172 
173 	return enable_fec_anatop_clock(0, ENET_125MHZ);
174 }
175 
176 int board_eth_init(bd_t *bis)
177 {
178 	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
179 	setup_fec();
180 
181 	return cpu_eth_init(bis);
182 }
183 
184 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
185 /* I2C1 for PMIC */
186 static struct i2c_pads_info i2c_pad_info1 = {
187 	.scl = {
188 		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
189 		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
190 		.gp = IMX_GPIO_NR(1, 0),
191 	},
192 	.sda = {
193 		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
194 		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
195 		.gp = IMX_GPIO_NR(1, 1),
196 	},
197 };
198 
199 int power_init_board(void)
200 {
201 	struct pmic *p;
202 	unsigned int reg;
203 	int ret;
204 
205 	p = pfuze_common_init(I2C_PMIC);
206 	if (!p)
207 		return -ENODEV;
208 
209 	ret = pfuze_mode_init(p, APS_PFM);
210 	if (ret < 0)
211 		return ret;
212 
213 	/* Enable power of VGEN5 3V3, needed for SD3 */
214 	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
215 	reg &= ~LDO_VOL_MASK;
216 	reg |= (LDOB_3_30V | (1 << LDO_EN));
217 	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
218 
219 	return 0;
220 }
221 
222 #ifdef CONFIG_USB_EHCI_MX6
223 #define USB_OTHERREGS_OFFSET	0x800
224 #define UCTRL_PWR_POL		(1 << 9)
225 
226 static iomux_v3_cfg_t const usb_otg_pads[] = {
227 	/* OGT1 */
228 	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
229 	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
230 	/* OTG2 */
231 	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
232 };
233 
234 static void setup_usb(void)
235 {
236 	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
237 					 ARRAY_SIZE(usb_otg_pads));
238 }
239 
240 int board_usb_phy_mode(int port)
241 {
242 	if (port == 1)
243 		return USB_INIT_HOST;
244 	else
245 		return usb_phy_mode(port);
246 }
247 
248 int board_ehci_hcd_init(int port)
249 {
250 	u32 *usbnc_usb_ctrl;
251 
252 	if (port > 1)
253 		return -EINVAL;
254 
255 	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
256 				 port * 4);
257 
258 	/* Set Power polarity */
259 	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
260 
261 	return 0;
262 }
263 #endif
264 
265 int board_phy_config(struct phy_device *phydev)
266 {
267 	/*
268 	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
269 	 * Phy control debug reg 0
270 	 */
271 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
272 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
273 
274 	/* rgmii tx clock delay enable */
275 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
276 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
277 
278 	if (phydev->drv->config)
279 		phydev->drv->config(phydev);
280 
281 	return 0;
282 }
283 
284 int board_early_init_f(void)
285 {
286 	setup_iomux_uart();
287 
288 	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
289 	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
290 					 ARRAY_SIZE(peri_3v3_pads));
291 
292 	/* Active high for ncp692 */
293 	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
294 
295 #ifdef CONFIG_USB_EHCI_MX6
296 	setup_usb();
297 #endif
298 
299 	return 0;
300 }
301 
302 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
303 	{USDHC2_BASE_ADDR, 0, 4},
304 	{USDHC3_BASE_ADDR},
305 	{USDHC4_BASE_ADDR},
306 };
307 
308 #define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 10)
309 #define USDHC3_PWR_GPIO	IMX_GPIO_NR(2, 11)
310 #define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 21)
311 
312 int board_mmc_getcd(struct mmc *mmc)
313 {
314 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
315 	int ret = 0;
316 
317 	switch (cfg->esdhc_base) {
318 	case USDHC2_BASE_ADDR:
319 		ret = 1; /* Assume uSDHC2 is always present */
320 		break;
321 	case USDHC3_BASE_ADDR:
322 		ret = !gpio_get_value(USDHC3_CD_GPIO);
323 		break;
324 	case USDHC4_BASE_ADDR:
325 		ret = !gpio_get_value(USDHC4_CD_GPIO);
326 		break;
327 	}
328 
329 	return ret;
330 }
331 
332 int board_mmc_init(bd_t *bis)
333 {
334 #ifndef CONFIG_SPL_BUILD
335 	int i, ret;
336 
337 	/*
338 	 * According to the board_mmc_init() the following map is done:
339 	 * (U-boot device node)    (Physical Port)
340 	 * mmc0                    USDHC2
341 	 * mmc1                    USDHC3
342 	 * mmc2                    USDHC4
343 	 */
344 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
345 		switch (i) {
346 		case 0:
347 			imx_iomux_v3_setup_multiple_pads(
348 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
349 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
350 			break;
351 		case 1:
352 			imx_iomux_v3_setup_multiple_pads(
353 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
354 			gpio_direction_input(USDHC3_CD_GPIO);
355 			gpio_direction_output(USDHC3_PWR_GPIO, 1);
356 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
357 			break;
358 		case 2:
359 			imx_iomux_v3_setup_multiple_pads(
360 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
361 			gpio_direction_input(USDHC4_CD_GPIO);
362 			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
363 			break;
364 		default:
365 			printf("Warning: you configured more USDHC controllers"
366 				"(%d) than supported by the board\n", i + 1);
367 			return -EINVAL;
368 			}
369 
370 			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
371 			if (ret) {
372 				printf("Warning: failed to initialize mmc dev %d\n", i);
373 				return ret;
374 			}
375 	}
376 
377 	return 0;
378 #else
379 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
380 	u32 val;
381 	u32 port;
382 
383 	val = readl(&src_regs->sbmr1);
384 
385 	if ((val & 0xc0) != 0x40) {
386 		printf("Not boot from USDHC!\n");
387 		return -EINVAL;
388 	}
389 
390 	port = (val >> 11) & 0x3;
391 	printf("port %d\n", port);
392 	switch (port) {
393 	case 1:
394 		imx_iomux_v3_setup_multiple_pads(
395 			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
396 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
397 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
398 		break;
399 	case 2:
400 		imx_iomux_v3_setup_multiple_pads(
401 			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
402 		gpio_direction_input(USDHC3_CD_GPIO);
403 		gpio_direction_output(USDHC3_PWR_GPIO, 1);
404 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
405 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
406 		break;
407 	case 3:
408 		imx_iomux_v3_setup_multiple_pads(
409 			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
410 		gpio_direction_input(USDHC4_CD_GPIO);
411 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
412 		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
413 		break;
414 	}
415 
416 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
417 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
418 #endif
419 }
420 
421 #ifdef CONFIG_FSL_QSPI
422 
423 #define QSPI_PAD_CTRL1	\
424 	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
425 	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
426 
427 static iomux_v3_cfg_t const quadspi_pads[] = {
428 	MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
429 	MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
430 	MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
431 	MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
432 	MX6_PAD_NAND_ALE__QSPI2_A_SS0_B		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
433 	MX6_PAD_NAND_CLE__QSPI2_A_SCLK		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
434 	MX6_PAD_NAND_DATA07__QSPI2_A_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
435 	MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
436 	MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
437 	MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
438 	MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
439 	MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
440 	MX6_PAD_NAND_DATA02__QSPI2_B_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
441 	MX6_PAD_NAND_DATA05__QSPI2_B_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
442 };
443 
444 int board_qspi_init(void)
445 {
446 	/* Set the iomux */
447 	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
448 					 ARRAY_SIZE(quadspi_pads));
449 
450 	/* Set the clock */
451 	enable_qspi_clk(1);
452 
453 	return 0;
454 }
455 #endif
456 
457 int board_init(void)
458 {
459 	/* Address of boot parameters */
460 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
461 
462 #ifdef CONFIG_SYS_I2C_MXC
463 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
464 #endif
465 
466 #ifdef CONFIG_FSL_QSPI
467 	board_qspi_init();
468 #endif
469 
470 	return 0;
471 }
472 
473 int checkboard(void)
474 {
475 	puts("Board: MX6SX SABRE SDB\n");
476 
477 	return 0;
478 }
479 
480 #ifdef CONFIG_SPL_BUILD
481 #include <libfdt.h>
482 #include <spl.h>
483 #include <asm/arch/mx6-ddr.h>
484 
485 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
486 	.dram_dqm0 = 0x00000028,
487 	.dram_dqm1 = 0x00000028,
488 	.dram_dqm2 = 0x00000028,
489 	.dram_dqm3 = 0x00000028,
490 	.dram_ras = 0x00000020,
491 	.dram_cas = 0x00000020,
492 	.dram_odt0 = 0x00000020,
493 	.dram_odt1 = 0x00000020,
494 	.dram_sdba2 = 0x00000000,
495 	.dram_sdcke0 = 0x00003000,
496 	.dram_sdcke1 = 0x00003000,
497 	.dram_sdclk_0 = 0x00000030,
498 	.dram_sdqs0 = 0x00000028,
499 	.dram_sdqs1 = 0x00000028,
500 	.dram_sdqs2 = 0x00000028,
501 	.dram_sdqs3 = 0x00000028,
502 	.dram_reset = 0x00000020,
503 };
504 
505 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
506 	.grp_addds = 0x00000020,
507 	.grp_ddrmode_ctl = 0x00020000,
508 	.grp_ddrpke = 0x00000000,
509 	.grp_ddrmode = 0x00020000,
510 	.grp_b0ds = 0x00000028,
511 	.grp_b1ds = 0x00000028,
512 	.grp_ctlds = 0x00000020,
513 	.grp_ddr_type = 0x000c0000,
514 	.grp_b2ds = 0x00000028,
515 	.grp_b3ds = 0x00000028,
516 };
517 
518 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
519 	.p0_mpwldectrl0 = 0x00290025,
520 	.p0_mpwldectrl1 = 0x00220022,
521 	.p0_mpdgctrl0 = 0x41480144,
522 	.p0_mpdgctrl1 = 0x01340130,
523 	.p0_mprddlctl = 0x3C3E4244,
524 	.p0_mpwrdlctl = 0x34363638,
525 };
526 
527 static struct mx6_ddr3_cfg mem_ddr = {
528 	.mem_speed = 1600,
529 	.density = 4,
530 	.width = 32,
531 	.banks = 8,
532 	.rowaddr = 15,
533 	.coladdr = 10,
534 	.pagesz = 2,
535 	.trcd = 1375,
536 	.trcmin = 4875,
537 	.trasmin = 3500,
538 };
539 
540 static void ccgr_init(void)
541 {
542 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
543 
544 	writel(0xFFFFFFFF, &ccm->CCGR0);
545 	writel(0xFFFFFFFF, &ccm->CCGR1);
546 	writel(0xFFFFFFFF, &ccm->CCGR2);
547 	writel(0xFFFFFFFF, &ccm->CCGR3);
548 	writel(0xFFFFFFFF, &ccm->CCGR4);
549 	writel(0xFFFFFFFF, &ccm->CCGR5);
550 	writel(0xFFFFFFFF, &ccm->CCGR6);
551 	writel(0xFFFFFFFF, &ccm->CCGR7);
552 }
553 
554 static void spl_dram_init(void)
555 {
556 	struct mx6_ddr_sysinfo sysinfo = {
557 		.dsize = mem_ddr.width/32,
558 		.cs_density = 24,
559 		.ncs = 1,
560 		.cs1_mirror = 0,
561 		.rtt_wr = 2,
562 		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
563 		.walat = 1,		/* Write additional latency */
564 		.ralat = 5,		/* Read additional latency */
565 		.mif3_mode = 3,		/* Command prediction working mode */
566 		.bi_on = 1,		/* Bank interleaving enabled */
567 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
568 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
569 		.ddr_type = DDR_TYPE_DDR3,
570 	};
571 
572 	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
573 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
574 }
575 
576 void board_init_f(ulong dummy)
577 {
578 	/* setup AIPS and disable watchdog */
579 	arch_cpu_init();
580 
581 	ccgr_init();
582 
583 	/* iomux and setup of i2c */
584 	board_early_init_f();
585 
586 	/* setup GP timer */
587 	timer_init();
588 
589 	/* UART clocks enabled and gd valid - init serial console */
590 	preloader_console_init();
591 
592 	/* DDR initialization */
593 	spl_dram_init();
594 
595 	/* Clear the BSS. */
596 	memset(__bss_start, 0, __bss_end - __bss_start);
597 
598 	/* load/boot image from boot device */
599 	board_init_r(NULL, 0);
600 }
601 
602 void reset_cpu(ulong addr)
603 {
604 }
605 #endif
606