1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/gpio.h> 16 #include <asm/mach-imx/iomux-v3.h> 17 #include <asm/io.h> 18 #include <asm/mach-imx/mxc_i2c.h> 19 #include <linux/sizes.h> 20 #include <common.h> 21 #include <fsl_esdhc.h> 22 #include <mmc.h> 23 #include <i2c.h> 24 #include <miiphy.h> 25 #include <netdev.h> 26 #include <power/pmic.h> 27 #include <power/pfuze100_pmic.h> 28 #include "../common/pfuze.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 33 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 35 36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 37 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 38 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 41 PAD_CTL_SPEED_HIGH | \ 42 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 43 44 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ 45 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) 46 47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 48 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 49 50 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 51 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 52 53 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ 54 PAD_CTL_DSE_40ohm) 55 56 int dram_init(void) 57 { 58 gd->ram_size = imx_ddr_size(); 59 60 return 0; 61 } 62 63 static iomux_v3_cfg_t const uart1_pads[] = { 64 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 65 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 66 }; 67 68 static iomux_v3_cfg_t const wdog_b_pad = { 69 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), 70 }; 71 static iomux_v3_cfg_t const fec1_pads[] = { 72 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 75 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 76 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 77 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 78 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 79 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 80 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 }; 87 88 static iomux_v3_cfg_t const peri_3v3_pads[] = { 89 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 90 }; 91 92 static iomux_v3_cfg_t const phy_control_pads[] = { 93 /* 25MHz Ethernet PHY Clock */ 94 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 95 96 /* ENET PHY Power */ 97 MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), 98 99 /* AR8031 PHY Reset */ 100 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 101 }; 102 103 static void setup_iomux_uart(void) 104 { 105 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 106 } 107 108 static int setup_fec(void) 109 { 110 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 111 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 112 int reg, ret; 113 114 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ 115 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); 116 117 ret = enable_fec_anatop_clock(0, ENET_125MHZ); 118 if (ret) 119 return ret; 120 121 imx_iomux_v3_setup_multiple_pads(phy_control_pads, 122 ARRAY_SIZE(phy_control_pads)); 123 124 /* Enable the ENET power, active low */ 125 gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); 126 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); 127 128 /* Reset AR8031 PHY */ 129 gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); 130 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); 131 mdelay(10); 132 gpio_set_value(IMX_GPIO_NR(2, 7), 1); 133 134 reg = readl(&anatop->pll_enet); 135 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; 136 writel(reg, &anatop->pll_enet); 137 138 return 0; 139 } 140 141 int board_eth_init(bd_t *bis) 142 { 143 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 144 setup_fec(); 145 146 return cpu_eth_init(bis); 147 } 148 149 int power_init_board(void) 150 { 151 struct udevice *dev; 152 unsigned int reg; 153 int ret; 154 155 dev = pfuze_common_init(); 156 if (!dev) 157 return -ENODEV; 158 159 ret = pfuze_mode_init(dev, APS_PFM); 160 if (ret < 0) 161 return ret; 162 163 /* Enable power of VGEN5 3V3, needed for SD3 */ 164 reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); 165 reg &= ~LDO_VOL_MASK; 166 reg |= (LDOB_3_30V | (1 << LDO_EN)); 167 pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); 168 169 return 0; 170 } 171 172 int board_phy_config(struct phy_device *phydev) 173 { 174 /* 175 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on 176 * Phy control debug reg 0 177 */ 178 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 179 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 180 181 /* rgmii tx clock delay enable */ 182 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 183 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 184 185 if (phydev->drv->config) 186 phydev->drv->config(phydev); 187 188 return 0; 189 } 190 191 int board_early_init_f(void) 192 { 193 setup_iomux_uart(); 194 195 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 196 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, 197 ARRAY_SIZE(peri_3v3_pads)); 198 199 return 0; 200 } 201 202 int board_mmc_get_env_dev(int devno) 203 { 204 return devno; 205 } 206 207 #ifdef CONFIG_FSL_QSPI 208 209 #define QSPI_PAD_CTRL1 \ 210 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ 211 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) 212 213 static iomux_v3_cfg_t const quadspi_pads[] = { 214 MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 215 MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 216 MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 217 MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 218 MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 219 MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 220 MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 221 MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 222 MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 223 MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 224 MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 225 MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 226 MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 227 MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 228 }; 229 230 int board_qspi_init(void) 231 { 232 /* Set the iomux */ 233 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 234 ARRAY_SIZE(quadspi_pads)); 235 236 /* Set the clock */ 237 enable_qspi_clk(1); 238 239 return 0; 240 } 241 #endif 242 243 #ifdef CONFIG_VIDEO_MXS 244 static iomux_v3_cfg_t const lcd_pads[] = { 245 MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 246 MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 247 MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 248 MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 249 MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 250 MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 251 MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 252 MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 253 MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 254 MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 255 MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 256 MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 257 MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 258 MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 259 MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 260 MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 261 MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 262 MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 263 MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 264 MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 265 MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 266 MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 267 MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 268 MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 269 MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 270 MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 271 MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 272 MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 273 MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), 274 275 /* Use GPIO for Brightness adjustment, duty cycle = period */ 276 MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL), 277 }; 278 279 static int setup_lcd(void) 280 { 281 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); 282 283 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 284 285 /* Reset the LCD */ 286 gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst"); 287 gpio_direction_output(IMX_GPIO_NR(3, 27) , 0); 288 udelay(500); 289 gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); 290 291 /* Set Brightness to high */ 292 gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright"); 293 gpio_direction_output(IMX_GPIO_NR(6, 4) , 1); 294 295 return 0; 296 } 297 #endif 298 299 int board_init(void) 300 { 301 /* Address of boot parameters */ 302 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 303 304 /* 305 * Because kernel set WDOG_B mux before pad with the common pinctrl 306 * framwork now and wdog reset will be triggered once set WDOG_B mux 307 * with default pad setting, we set pad setting here to workaround this. 308 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set 309 * as GPIO mux firstly here to workaround it. 310 */ 311 imx_iomux_v3_setup_pad(wdog_b_pad); 312 313 /* Active high for ncp692 */ 314 gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en"); 315 gpio_direction_output(IMX_GPIO_NR(4, 16), 1); 316 317 #ifdef CONFIG_FSL_QSPI 318 board_qspi_init(); 319 #endif 320 321 #ifdef CONFIG_VIDEO_MXS 322 setup_lcd(); 323 #endif 324 325 return 0; 326 } 327 328 static bool is_reva(void) 329 { 330 return (nxp_board_rev() == 1); 331 } 332 333 int board_late_init(void) 334 { 335 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 336 if (is_reva()) 337 env_set("board_rev", "REVA"); 338 #endif 339 return 0; 340 } 341 342 int checkboard(void) 343 { 344 printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string()); 345 346 return 0; 347 } 348 349 #ifdef CONFIG_SPL_BUILD 350 #include <linux/libfdt.h> 351 #include <spl.h> 352 #include <asm/arch/mx6-ddr.h> 353 354 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 355 {USDHC2_BASE_ADDR, 0, 4}, 356 {USDHC3_BASE_ADDR}, 357 {USDHC4_BASE_ADDR}, 358 }; 359 360 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) 361 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) 362 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) 363 364 static iomux_v3_cfg_t const usdhc2_pads[] = { 365 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 366 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 367 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 368 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 369 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 370 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 371 }; 372 373 static iomux_v3_cfg_t const usdhc3_pads[] = { 374 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 375 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 376 MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 377 MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 378 MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 379 MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 380 MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 381 MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 382 MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 383 MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 384 385 /* CD pin */ 386 MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), 387 388 /* RST_B, used for power reset cycle */ 389 MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), 390 }; 391 392 static iomux_v3_cfg_t const usdhc4_pads[] = { 393 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 394 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 395 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 396 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 397 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 398 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 399 MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 400 }; 401 402 int board_mmc_init(bd_t *bis) 403 { 404 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 405 u32 val; 406 u32 port; 407 408 val = readl(&src_regs->sbmr1); 409 410 if ((val & 0xc0) != 0x40) { 411 printf("Not boot from USDHC!\n"); 412 return -EINVAL; 413 } 414 415 port = (val >> 11) & 0x3; 416 printf("port %d\n", port); 417 switch (port) { 418 case 1: 419 imx_iomux_v3_setup_multiple_pads( 420 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 421 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 422 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 423 break; 424 case 2: 425 imx_iomux_v3_setup_multiple_pads( 426 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 427 gpio_direction_input(USDHC3_CD_GPIO); 428 gpio_direction_output(USDHC3_PWR_GPIO, 1); 429 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 430 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 431 break; 432 case 3: 433 imx_iomux_v3_setup_multiple_pads( 434 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 435 gpio_direction_input(USDHC4_CD_GPIO); 436 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 437 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 438 break; 439 } 440 441 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 442 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 443 } 444 445 int board_mmc_getcd(struct mmc *mmc) 446 { 447 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 448 int ret = 0; 449 450 switch (cfg->esdhc_base) { 451 case USDHC2_BASE_ADDR: 452 ret = 1; /* Assume uSDHC2 is always present */ 453 break; 454 case USDHC3_BASE_ADDR: 455 ret = !gpio_get_value(USDHC3_CD_GPIO); 456 break; 457 case USDHC4_BASE_ADDR: 458 ret = !gpio_get_value(USDHC4_CD_GPIO); 459 break; 460 } 461 462 return ret; 463 } 464 465 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { 466 .dram_dqm0 = 0x00000028, 467 .dram_dqm1 = 0x00000028, 468 .dram_dqm2 = 0x00000028, 469 .dram_dqm3 = 0x00000028, 470 .dram_ras = 0x00000020, 471 .dram_cas = 0x00000020, 472 .dram_odt0 = 0x00000020, 473 .dram_odt1 = 0x00000020, 474 .dram_sdba2 = 0x00000000, 475 .dram_sdcke0 = 0x00003000, 476 .dram_sdcke1 = 0x00003000, 477 .dram_sdclk_0 = 0x00000030, 478 .dram_sdqs0 = 0x00000028, 479 .dram_sdqs1 = 0x00000028, 480 .dram_sdqs2 = 0x00000028, 481 .dram_sdqs3 = 0x00000028, 482 .dram_reset = 0x00000020, 483 }; 484 485 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { 486 .grp_addds = 0x00000020, 487 .grp_ddrmode_ctl = 0x00020000, 488 .grp_ddrpke = 0x00000000, 489 .grp_ddrmode = 0x00020000, 490 .grp_b0ds = 0x00000028, 491 .grp_b1ds = 0x00000028, 492 .grp_ctlds = 0x00000020, 493 .grp_ddr_type = 0x000c0000, 494 .grp_b2ds = 0x00000028, 495 .grp_b3ds = 0x00000028, 496 }; 497 498 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 499 .p0_mpwldectrl0 = 0x00290025, 500 .p0_mpwldectrl1 = 0x00220022, 501 .p0_mpdgctrl0 = 0x41480144, 502 .p0_mpdgctrl1 = 0x01340130, 503 .p0_mprddlctl = 0x3C3E4244, 504 .p0_mpwrdlctl = 0x34363638, 505 }; 506 507 static struct mx6_ddr3_cfg mem_ddr = { 508 .mem_speed = 1600, 509 .density = 4, 510 .width = 32, 511 .banks = 8, 512 .rowaddr = 15, 513 .coladdr = 10, 514 .pagesz = 2, 515 .trcd = 1375, 516 .trcmin = 4875, 517 .trasmin = 3500, 518 }; 519 520 static void ccgr_init(void) 521 { 522 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 523 524 writel(0xFFFFFFFF, &ccm->CCGR0); 525 writel(0xFFFFFFFF, &ccm->CCGR1); 526 writel(0xFFFFFFFF, &ccm->CCGR2); 527 writel(0xFFFFFFFF, &ccm->CCGR3); 528 writel(0xFFFFFFFF, &ccm->CCGR4); 529 writel(0xFFFFFFFF, &ccm->CCGR5); 530 writel(0xFFFFFFFF, &ccm->CCGR6); 531 writel(0xFFFFFFFF, &ccm->CCGR7); 532 } 533 534 static void spl_dram_init(void) 535 { 536 struct mx6_ddr_sysinfo sysinfo = { 537 .dsize = mem_ddr.width/32, 538 .cs_density = 24, 539 .ncs = 1, 540 .cs1_mirror = 0, 541 .rtt_wr = 2, 542 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 543 .walat = 1, /* Write additional latency */ 544 .ralat = 5, /* Read additional latency */ 545 .mif3_mode = 3, /* Command prediction working mode */ 546 .bi_on = 1, /* Bank interleaving enabled */ 547 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 548 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 549 .ddr_type = DDR_TYPE_DDR3, 550 .refsel = 1, /* Refresh cycles at 32KHz */ 551 .refr = 7, /* 8 refresh commands per refresh cycle */ 552 }; 553 554 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 555 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 556 } 557 558 void board_init_f(ulong dummy) 559 { 560 /* setup AIPS and disable watchdog */ 561 arch_cpu_init(); 562 563 ccgr_init(); 564 565 /* iomux and setup of i2c */ 566 board_early_init_f(); 567 568 /* setup GP timer */ 569 timer_init(); 570 571 /* UART clocks enabled and gd valid - init serial console */ 572 preloader_console_init(); 573 574 /* DDR initialization */ 575 spl_dram_init(); 576 577 /* Clear the BSS. */ 578 memset(__bss_start, 0, __bss_end - __bss_start); 579 580 /* load/boot image from boot device */ 581 board_init_r(NULL, 0); 582 } 583 #endif 584