1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/gpio.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/io.h> 18 #include <asm/imx-common/mxc_i2c.h> 19 #include <linux/sizes.h> 20 #include <common.h> 21 #include <fsl_esdhc.h> 22 #include <mmc.h> 23 #include <i2c.h> 24 #include <miiphy.h> 25 #include <netdev.h> 26 #include <power/pmic.h> 27 #include <power/pfuze100_pmic.h> 28 #include "../common/pfuze.h" 29 #include <usb.h> 30 #include <usb/ehci-fsl.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 37 38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 42 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 43 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 44 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 45 PAD_CTL_ODE) 46 47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 48 PAD_CTL_SPEED_HIGH | \ 49 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 50 51 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ 52 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) 53 54 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 56 57 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 58 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 59 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 60 PAD_CTL_ODE) 61 62 int dram_init(void) 63 { 64 gd->ram_size = PHYS_SDRAM_SIZE; 65 66 return 0; 67 } 68 69 static iomux_v3_cfg_t const uart1_pads[] = { 70 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 71 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 72 }; 73 74 static iomux_v3_cfg_t const usdhc2_pads[] = { 75 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 }; 82 83 static iomux_v3_cfg_t const usdhc3_pads[] = { 84 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 95 /* CD pin */ 96 MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), 97 98 /* RST_B, used for power reset cycle */ 99 MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), 100 }; 101 102 static iomux_v3_cfg_t const usdhc4_pads[] = { 103 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 110 }; 111 112 static iomux_v3_cfg_t const fec1_pads[] = { 113 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 114 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 115 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 116 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 117 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 118 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 119 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 120 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 121 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 122 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 123 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 124 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 125 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 126 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 127 }; 128 129 static iomux_v3_cfg_t const peri_3v3_pads[] = { 130 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 131 }; 132 133 static iomux_v3_cfg_t const phy_control_pads[] = { 134 /* 25MHz Ethernet PHY Clock */ 135 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 136 137 /* ENET PHY Power */ 138 MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), 139 140 /* AR8031 PHY Reset */ 141 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 142 }; 143 144 static void setup_iomux_uart(void) 145 { 146 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 147 } 148 149 static int setup_fec(void) 150 { 151 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 152 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 153 int reg; 154 155 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ 156 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); 157 158 imx_iomux_v3_setup_multiple_pads(phy_control_pads, 159 ARRAY_SIZE(phy_control_pads)); 160 161 /* Enable the ENET power, active low */ 162 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); 163 164 /* Reset AR8031 PHY */ 165 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); 166 udelay(500); 167 gpio_set_value(IMX_GPIO_NR(2, 7), 1); 168 169 reg = readl(&anatop->pll_enet); 170 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; 171 writel(reg, &anatop->pll_enet); 172 173 return enable_fec_anatop_clock(ENET_125MHZ); 174 } 175 176 int board_eth_init(bd_t *bis) 177 { 178 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 179 setup_fec(); 180 181 return cpu_eth_init(bis); 182 } 183 184 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 185 /* I2C1 for PMIC */ 186 static struct i2c_pads_info i2c_pad_info1 = { 187 .scl = { 188 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, 189 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, 190 .gp = IMX_GPIO_NR(1, 0), 191 }, 192 .sda = { 193 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, 194 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, 195 .gp = IMX_GPIO_NR(1, 1), 196 }, 197 }; 198 199 int power_init_board(void) 200 { 201 struct pmic *p; 202 unsigned int reg; 203 204 p = pfuze_common_init(I2C_PMIC); 205 if (!p) 206 return -ENODEV; 207 208 /* Enable power of VGEN5 3V3, needed for SD3 */ 209 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 210 reg &= ~LDO_VOL_MASK; 211 reg |= (LDOB_3_30V | (1 << LDO_EN)); 212 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 213 214 return 0; 215 } 216 217 #ifdef CONFIG_USB_EHCI_MX6 218 #define USB_OTHERREGS_OFFSET 0x800 219 #define UCTRL_PWR_POL (1 << 9) 220 221 static iomux_v3_cfg_t const usb_otg_pads[] = { 222 /* OGT1 */ 223 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 224 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 225 /* OTG2 */ 226 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) 227 }; 228 229 static void setup_usb(void) 230 { 231 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 232 ARRAY_SIZE(usb_otg_pads)); 233 } 234 235 int board_usb_phy_mode(int port) 236 { 237 if (port == 1) 238 return USB_INIT_HOST; 239 else 240 return usb_phy_mode(port); 241 } 242 243 int board_ehci_hcd_init(int port) 244 { 245 u32 *usbnc_usb_ctrl; 246 247 if (port > 1) 248 return -EINVAL; 249 250 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 251 port * 4); 252 253 /* Set Power polarity */ 254 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 255 256 return 0; 257 } 258 #endif 259 260 int board_phy_config(struct phy_device *phydev) 261 { 262 /* 263 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on 264 * Phy control debug reg 0 265 */ 266 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 267 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 268 269 /* rgmii tx clock delay enable */ 270 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 271 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 272 273 if (phydev->drv->config) 274 phydev->drv->config(phydev); 275 276 return 0; 277 } 278 279 int board_early_init_f(void) 280 { 281 setup_iomux_uart(); 282 283 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 284 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, 285 ARRAY_SIZE(peri_3v3_pads)); 286 287 /* Active high for ncp692 */ 288 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); 289 290 #ifdef CONFIG_USB_EHCI_MX6 291 setup_usb(); 292 #endif 293 294 return 0; 295 } 296 297 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 298 {USDHC2_BASE_ADDR, 0, 4}, 299 {USDHC3_BASE_ADDR}, 300 {USDHC4_BASE_ADDR}, 301 }; 302 303 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) 304 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) 305 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) 306 307 int board_mmc_getcd(struct mmc *mmc) 308 { 309 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 310 int ret = 0; 311 312 switch (cfg->esdhc_base) { 313 case USDHC2_BASE_ADDR: 314 ret = 1; /* Assume uSDHC2 is always present */ 315 break; 316 case USDHC3_BASE_ADDR: 317 ret = !gpio_get_value(USDHC3_CD_GPIO); 318 break; 319 case USDHC4_BASE_ADDR: 320 ret = !gpio_get_value(USDHC4_CD_GPIO); 321 break; 322 } 323 324 return ret; 325 } 326 327 int board_mmc_init(bd_t *bis) 328 { 329 #ifndef CONFIG_SPL_BUILD 330 int i, ret; 331 332 /* 333 * According to the board_mmc_init() the following map is done: 334 * (U-boot device node) (Physical Port) 335 * mmc0 USDHC2 336 * mmc1 USDHC3 337 * mmc2 USDHC4 338 */ 339 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 340 switch (i) { 341 case 0: 342 imx_iomux_v3_setup_multiple_pads( 343 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 344 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 345 break; 346 case 1: 347 imx_iomux_v3_setup_multiple_pads( 348 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 349 gpio_direction_input(USDHC3_CD_GPIO); 350 gpio_direction_output(USDHC3_PWR_GPIO, 1); 351 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 352 break; 353 case 2: 354 imx_iomux_v3_setup_multiple_pads( 355 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 356 gpio_direction_input(USDHC4_CD_GPIO); 357 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 358 break; 359 default: 360 printf("Warning: you configured more USDHC controllers" 361 "(%d) than supported by the board\n", i + 1); 362 return -EINVAL; 363 } 364 365 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 366 if (ret) { 367 printf("Warning: failed to initialize mmc dev %d\n", i); 368 return ret; 369 } 370 } 371 372 return 0; 373 #else 374 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 375 u32 val; 376 u32 port; 377 378 val = readl(&src_regs->sbmr1); 379 380 if ((val & 0xc0) != 0x40) { 381 printf("Not boot from USDHC!\n"); 382 return -EINVAL; 383 } 384 385 port = (val >> 11) & 0x3; 386 printf("port %d\n", port); 387 switch (port) { 388 case 1: 389 imx_iomux_v3_setup_multiple_pads( 390 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 391 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 392 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 393 break; 394 case 2: 395 imx_iomux_v3_setup_multiple_pads( 396 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 397 gpio_direction_input(USDHC3_CD_GPIO); 398 gpio_direction_output(USDHC3_PWR_GPIO, 1); 399 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 400 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 401 break; 402 case 3: 403 imx_iomux_v3_setup_multiple_pads( 404 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 405 gpio_direction_input(USDHC4_CD_GPIO); 406 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 407 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 408 break; 409 } 410 411 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 412 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 413 #endif 414 } 415 416 #ifdef CONFIG_FSL_QSPI 417 418 #define QSPI_PAD_CTRL1 \ 419 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ 420 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) 421 422 static iomux_v3_cfg_t const quadspi_pads[] = { 423 MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 424 MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 425 MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 426 MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 427 MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 428 MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 429 MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 430 MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 431 MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 432 MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 433 MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 434 MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 435 MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 436 MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 437 }; 438 439 int board_qspi_init(void) 440 { 441 /* Set the iomux */ 442 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 443 ARRAY_SIZE(quadspi_pads)); 444 445 /* Set the clock */ 446 enable_qspi_clk(1); 447 448 return 0; 449 } 450 #endif 451 452 int board_init(void) 453 { 454 /* Address of boot parameters */ 455 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 456 457 #ifdef CONFIG_SYS_I2C_MXC 458 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 459 #endif 460 461 #ifdef CONFIG_FSL_QSPI 462 board_qspi_init(); 463 #endif 464 465 return 0; 466 } 467 468 int checkboard(void) 469 { 470 puts("Board: MX6SX SABRE SDB\n"); 471 472 return 0; 473 } 474 475 #ifdef CONFIG_SPL_BUILD 476 #include <libfdt.h> 477 #include <spl.h> 478 #include <asm/arch/mx6-ddr.h> 479 480 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { 481 .dram_dqm0 = 0x00000028, 482 .dram_dqm1 = 0x00000028, 483 .dram_dqm2 = 0x00000028, 484 .dram_dqm3 = 0x00000028, 485 .dram_ras = 0x00000020, 486 .dram_cas = 0x00000020, 487 .dram_odt0 = 0x00000020, 488 .dram_odt1 = 0x00000020, 489 .dram_sdba2 = 0x00000000, 490 .dram_sdcke0 = 0x00003000, 491 .dram_sdcke1 = 0x00003000, 492 .dram_sdclk_0 = 0x00000030, 493 .dram_sdqs0 = 0x00000028, 494 .dram_sdqs1 = 0x00000028, 495 .dram_sdqs2 = 0x00000028, 496 .dram_sdqs3 = 0x00000028, 497 .dram_reset = 0x00000020, 498 }; 499 500 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { 501 .grp_addds = 0x00000020, 502 .grp_ddrmode_ctl = 0x00020000, 503 .grp_ddrpke = 0x00000000, 504 .grp_ddrmode = 0x00020000, 505 .grp_b0ds = 0x00000028, 506 .grp_b1ds = 0x00000028, 507 .grp_ctlds = 0x00000020, 508 .grp_ddr_type = 0x000c0000, 509 .grp_b2ds = 0x00000028, 510 .grp_b3ds = 0x00000028, 511 }; 512 513 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 514 .p0_mpwldectrl0 = 0x00290025, 515 .p0_mpwldectrl1 = 0x00220022, 516 .p0_mpdgctrl0 = 0x41480144, 517 .p0_mpdgctrl1 = 0x01340130, 518 .p0_mprddlctl = 0x3C3E4244, 519 .p0_mpwrdlctl = 0x34363638, 520 }; 521 522 static struct mx6_ddr3_cfg mem_ddr = { 523 .mem_speed = 1600, 524 .density = 4, 525 .width = 32, 526 .banks = 8, 527 .rowaddr = 15, 528 .coladdr = 10, 529 .pagesz = 2, 530 .trcd = 1375, 531 .trcmin = 4875, 532 .trasmin = 3500, 533 }; 534 535 static void ccgr_init(void) 536 { 537 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 538 539 writel(0xFFFFFFFF, &ccm->CCGR0); 540 writel(0xFFFFFFFF, &ccm->CCGR1); 541 writel(0xFFFFFFFF, &ccm->CCGR2); 542 writel(0xFFFFFFFF, &ccm->CCGR3); 543 writel(0xFFFFFFFF, &ccm->CCGR4); 544 writel(0xFFFFFFFF, &ccm->CCGR5); 545 writel(0xFFFFFFFF, &ccm->CCGR6); 546 writel(0xFFFFFFFF, &ccm->CCGR7); 547 } 548 549 static void spl_dram_init(void) 550 { 551 struct mx6_ddr_sysinfo sysinfo = { 552 .dsize = mem_ddr.width/32, 553 .cs_density = 24, 554 .ncs = 1, 555 .cs1_mirror = 0, 556 .rtt_wr = 2, 557 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 558 .walat = 1, /* Write additional latency */ 559 .ralat = 5, /* Read additional latency */ 560 .mif3_mode = 3, /* Command prediction working mode */ 561 .bi_on = 1, /* Bank interleaving enabled */ 562 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 563 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 564 }; 565 566 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 567 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 568 } 569 570 void board_init_f(ulong dummy) 571 { 572 /* setup AIPS and disable watchdog */ 573 arch_cpu_init(); 574 575 ccgr_init(); 576 577 /* iomux and setup of i2c */ 578 board_early_init_f(); 579 580 /* setup GP timer */ 581 timer_init(); 582 583 /* UART clocks enabled and gd valid - init serial console */ 584 preloader_console_init(); 585 586 /* DDR initialization */ 587 spl_dram_init(); 588 589 /* Clear the BSS. */ 590 memset(__bss_start, 0, __bss_end - __bss_start); 591 592 /* load/boot image from boot device */ 593 board_init_r(NULL, 0); 594 } 595 596 void reset_cpu(ulong addr) 597 { 598 } 599 #endif 600