1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/gpio.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/io.h> 18 #include <asm/imx-common/mxc_i2c.h> 19 #include <linux/sizes.h> 20 #include <common.h> 21 #include <fsl_esdhc.h> 22 #include <mmc.h> 23 #include <i2c.h> 24 #include <miiphy.h> 25 #include <netdev.h> 26 #include <power/pmic.h> 27 #include <power/pfuze100_pmic.h> 28 #include "../common/pfuze.h" 29 #include <usb.h> 30 #include <usb/ehci-fsl.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 37 38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 42 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 43 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 44 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 45 PAD_CTL_ODE) 46 47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 48 PAD_CTL_SPEED_HIGH | \ 49 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 50 51 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ 52 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) 53 54 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 56 57 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 58 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 59 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 60 PAD_CTL_ODE) 61 62 int dram_init(void) 63 { 64 gd->ram_size = PHYS_SDRAM_SIZE; 65 66 return 0; 67 } 68 69 static iomux_v3_cfg_t const uart1_pads[] = { 70 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 71 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 72 }; 73 74 static iomux_v3_cfg_t const usdhc2_pads[] = { 75 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 }; 82 83 static iomux_v3_cfg_t const usdhc3_pads[] = { 84 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 95 /* CD pin */ 96 MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), 97 98 /* RST_B, used for power reset cycle */ 99 MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), 100 }; 101 102 static iomux_v3_cfg_t const usdhc4_pads[] = { 103 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 110 }; 111 112 static iomux_v3_cfg_t const fec1_pads[] = { 113 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 114 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 115 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 116 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 117 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 118 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 119 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 120 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 121 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 122 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 123 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 124 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 125 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 126 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 127 }; 128 129 static iomux_v3_cfg_t const peri_3v3_pads[] = { 130 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 131 }; 132 133 static iomux_v3_cfg_t const phy_control_pads[] = { 134 /* 25MHz Ethernet PHY Clock */ 135 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 136 137 /* ENET PHY Power */ 138 MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), 139 140 /* AR8031 PHY Reset */ 141 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 142 }; 143 144 static void setup_iomux_uart(void) 145 { 146 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 147 } 148 149 static int setup_fec(void) 150 { 151 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 152 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 153 int reg, ret; 154 155 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ 156 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); 157 158 ret = enable_fec_anatop_clock(0, ENET_125MHZ); 159 if (ret) 160 return ret; 161 162 imx_iomux_v3_setup_multiple_pads(phy_control_pads, 163 ARRAY_SIZE(phy_control_pads)); 164 165 /* Enable the ENET power, active low */ 166 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); 167 168 /* Reset AR8031 PHY */ 169 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); 170 mdelay(10); 171 gpio_set_value(IMX_GPIO_NR(2, 7), 1); 172 173 reg = readl(&anatop->pll_enet); 174 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; 175 writel(reg, &anatop->pll_enet); 176 177 return 0; 178 } 179 180 int board_eth_init(bd_t *bis) 181 { 182 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 183 setup_fec(); 184 185 return cpu_eth_init(bis); 186 } 187 188 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 189 /* I2C1 for PMIC */ 190 static struct i2c_pads_info i2c_pad_info1 = { 191 .scl = { 192 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, 193 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, 194 .gp = IMX_GPIO_NR(1, 0), 195 }, 196 .sda = { 197 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, 198 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, 199 .gp = IMX_GPIO_NR(1, 1), 200 }, 201 }; 202 203 int power_init_board(void) 204 { 205 struct pmic *p; 206 unsigned int reg; 207 int ret; 208 209 p = pfuze_common_init(I2C_PMIC); 210 if (!p) 211 return -ENODEV; 212 213 ret = pfuze_mode_init(p, APS_PFM); 214 if (ret < 0) 215 return ret; 216 217 /* Enable power of VGEN5 3V3, needed for SD3 */ 218 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 219 reg &= ~LDO_VOL_MASK; 220 reg |= (LDOB_3_30V | (1 << LDO_EN)); 221 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 222 223 return 0; 224 } 225 226 #ifdef CONFIG_USB_EHCI_MX6 227 #define USB_OTHERREGS_OFFSET 0x800 228 #define UCTRL_PWR_POL (1 << 9) 229 230 static iomux_v3_cfg_t const usb_otg_pads[] = { 231 /* OGT1 */ 232 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 233 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 234 /* OTG2 */ 235 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) 236 }; 237 238 static void setup_usb(void) 239 { 240 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 241 ARRAY_SIZE(usb_otg_pads)); 242 } 243 244 int board_usb_phy_mode(int port) 245 { 246 if (port == 1) 247 return USB_INIT_HOST; 248 else 249 return usb_phy_mode(port); 250 } 251 252 int board_ehci_hcd_init(int port) 253 { 254 u32 *usbnc_usb_ctrl; 255 256 if (port > 1) 257 return -EINVAL; 258 259 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 260 port * 4); 261 262 /* Set Power polarity */ 263 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 264 265 return 0; 266 } 267 #endif 268 269 int board_phy_config(struct phy_device *phydev) 270 { 271 /* 272 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on 273 * Phy control debug reg 0 274 */ 275 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 276 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 277 278 /* rgmii tx clock delay enable */ 279 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 280 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 281 282 if (phydev->drv->config) 283 phydev->drv->config(phydev); 284 285 return 0; 286 } 287 288 int board_early_init_f(void) 289 { 290 setup_iomux_uart(); 291 292 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 293 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, 294 ARRAY_SIZE(peri_3v3_pads)); 295 296 /* Active high for ncp692 */ 297 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); 298 299 #ifdef CONFIG_USB_EHCI_MX6 300 setup_usb(); 301 #endif 302 303 return 0; 304 } 305 306 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 307 {USDHC2_BASE_ADDR, 0, 4}, 308 {USDHC3_BASE_ADDR}, 309 {USDHC4_BASE_ADDR}, 310 }; 311 312 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) 313 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) 314 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) 315 316 int board_mmc_getcd(struct mmc *mmc) 317 { 318 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 319 int ret = 0; 320 321 switch (cfg->esdhc_base) { 322 case USDHC2_BASE_ADDR: 323 ret = 1; /* Assume uSDHC2 is always present */ 324 break; 325 case USDHC3_BASE_ADDR: 326 ret = !gpio_get_value(USDHC3_CD_GPIO); 327 break; 328 case USDHC4_BASE_ADDR: 329 ret = !gpio_get_value(USDHC4_CD_GPIO); 330 break; 331 } 332 333 return ret; 334 } 335 336 int board_mmc_init(bd_t *bis) 337 { 338 #ifndef CONFIG_SPL_BUILD 339 int i, ret; 340 341 /* 342 * According to the board_mmc_init() the following map is done: 343 * (U-boot device node) (Physical Port) 344 * mmc0 USDHC2 345 * mmc1 USDHC3 346 * mmc2 USDHC4 347 */ 348 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 349 switch (i) { 350 case 0: 351 imx_iomux_v3_setup_multiple_pads( 352 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 353 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 354 break; 355 case 1: 356 imx_iomux_v3_setup_multiple_pads( 357 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 358 gpio_direction_input(USDHC3_CD_GPIO); 359 gpio_direction_output(USDHC3_PWR_GPIO, 1); 360 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 361 break; 362 case 2: 363 imx_iomux_v3_setup_multiple_pads( 364 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 365 gpio_direction_input(USDHC4_CD_GPIO); 366 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 367 break; 368 default: 369 printf("Warning: you configured more USDHC controllers" 370 "(%d) than supported by the board\n", i + 1); 371 return -EINVAL; 372 } 373 374 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 375 if (ret) { 376 printf("Warning: failed to initialize mmc dev %d\n", i); 377 return ret; 378 } 379 } 380 381 return 0; 382 #else 383 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 384 u32 val; 385 u32 port; 386 387 val = readl(&src_regs->sbmr1); 388 389 if ((val & 0xc0) != 0x40) { 390 printf("Not boot from USDHC!\n"); 391 return -EINVAL; 392 } 393 394 port = (val >> 11) & 0x3; 395 printf("port %d\n", port); 396 switch (port) { 397 case 1: 398 imx_iomux_v3_setup_multiple_pads( 399 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 400 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 401 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 402 break; 403 case 2: 404 imx_iomux_v3_setup_multiple_pads( 405 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 406 gpio_direction_input(USDHC3_CD_GPIO); 407 gpio_direction_output(USDHC3_PWR_GPIO, 1); 408 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 409 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 410 break; 411 case 3: 412 imx_iomux_v3_setup_multiple_pads( 413 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 414 gpio_direction_input(USDHC4_CD_GPIO); 415 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 416 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 417 break; 418 } 419 420 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 421 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 422 #endif 423 } 424 425 #ifdef CONFIG_FSL_QSPI 426 427 #define QSPI_PAD_CTRL1 \ 428 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ 429 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) 430 431 static iomux_v3_cfg_t const quadspi_pads[] = { 432 MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 433 MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 434 MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 435 MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 436 MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 437 MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 438 MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 439 MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 440 MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 441 MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 442 MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 443 MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 444 MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 445 MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 446 }; 447 448 int board_qspi_init(void) 449 { 450 /* Set the iomux */ 451 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 452 ARRAY_SIZE(quadspi_pads)); 453 454 /* Set the clock */ 455 enable_qspi_clk(1); 456 457 return 0; 458 } 459 #endif 460 461 int board_init(void) 462 { 463 /* Address of boot parameters */ 464 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 465 466 #ifdef CONFIG_SYS_I2C_MXC 467 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 468 #endif 469 470 #ifdef CONFIG_FSL_QSPI 471 board_qspi_init(); 472 #endif 473 474 return 0; 475 } 476 477 int checkboard(void) 478 { 479 puts("Board: MX6SX SABRE SDB\n"); 480 481 return 0; 482 } 483 484 #ifdef CONFIG_SPL_BUILD 485 #include <libfdt.h> 486 #include <spl.h> 487 #include <asm/arch/mx6-ddr.h> 488 489 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { 490 .dram_dqm0 = 0x00000028, 491 .dram_dqm1 = 0x00000028, 492 .dram_dqm2 = 0x00000028, 493 .dram_dqm3 = 0x00000028, 494 .dram_ras = 0x00000020, 495 .dram_cas = 0x00000020, 496 .dram_odt0 = 0x00000020, 497 .dram_odt1 = 0x00000020, 498 .dram_sdba2 = 0x00000000, 499 .dram_sdcke0 = 0x00003000, 500 .dram_sdcke1 = 0x00003000, 501 .dram_sdclk_0 = 0x00000030, 502 .dram_sdqs0 = 0x00000028, 503 .dram_sdqs1 = 0x00000028, 504 .dram_sdqs2 = 0x00000028, 505 .dram_sdqs3 = 0x00000028, 506 .dram_reset = 0x00000020, 507 }; 508 509 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { 510 .grp_addds = 0x00000020, 511 .grp_ddrmode_ctl = 0x00020000, 512 .grp_ddrpke = 0x00000000, 513 .grp_ddrmode = 0x00020000, 514 .grp_b0ds = 0x00000028, 515 .grp_b1ds = 0x00000028, 516 .grp_ctlds = 0x00000020, 517 .grp_ddr_type = 0x000c0000, 518 .grp_b2ds = 0x00000028, 519 .grp_b3ds = 0x00000028, 520 }; 521 522 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 523 .p0_mpwldectrl0 = 0x00290025, 524 .p0_mpwldectrl1 = 0x00220022, 525 .p0_mpdgctrl0 = 0x41480144, 526 .p0_mpdgctrl1 = 0x01340130, 527 .p0_mprddlctl = 0x3C3E4244, 528 .p0_mpwrdlctl = 0x34363638, 529 }; 530 531 static struct mx6_ddr3_cfg mem_ddr = { 532 .mem_speed = 1600, 533 .density = 4, 534 .width = 32, 535 .banks = 8, 536 .rowaddr = 15, 537 .coladdr = 10, 538 .pagesz = 2, 539 .trcd = 1375, 540 .trcmin = 4875, 541 .trasmin = 3500, 542 }; 543 544 static void ccgr_init(void) 545 { 546 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 547 548 writel(0xFFFFFFFF, &ccm->CCGR0); 549 writel(0xFFFFFFFF, &ccm->CCGR1); 550 writel(0xFFFFFFFF, &ccm->CCGR2); 551 writel(0xFFFFFFFF, &ccm->CCGR3); 552 writel(0xFFFFFFFF, &ccm->CCGR4); 553 writel(0xFFFFFFFF, &ccm->CCGR5); 554 writel(0xFFFFFFFF, &ccm->CCGR6); 555 writel(0xFFFFFFFF, &ccm->CCGR7); 556 } 557 558 static void spl_dram_init(void) 559 { 560 struct mx6_ddr_sysinfo sysinfo = { 561 .dsize = mem_ddr.width/32, 562 .cs_density = 24, 563 .ncs = 1, 564 .cs1_mirror = 0, 565 .rtt_wr = 2, 566 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 567 .walat = 1, /* Write additional latency */ 568 .ralat = 5, /* Read additional latency */ 569 .mif3_mode = 3, /* Command prediction working mode */ 570 .bi_on = 1, /* Bank interleaving enabled */ 571 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 572 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 573 .ddr_type = DDR_TYPE_DDR3, 574 }; 575 576 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 577 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 578 } 579 580 void board_init_f(ulong dummy) 581 { 582 /* setup AIPS and disable watchdog */ 583 arch_cpu_init(); 584 585 ccgr_init(); 586 587 /* iomux and setup of i2c */ 588 board_early_init_f(); 589 590 /* setup GP timer */ 591 timer_init(); 592 593 /* UART clocks enabled and gd valid - init serial console */ 594 preloader_console_init(); 595 596 /* DDR initialization */ 597 spl_dram_init(); 598 599 /* Clear the BSS. */ 600 memset(__bss_start, 0, __bss_end - __bss_start); 601 602 /* load/boot image from boot device */ 603 board_init_r(NULL, 0); 604 } 605 #endif 606