1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#define __ASSEMBLY__
8#include <config.h>
9
10/* image version */
11
12IMAGE_VERSION 2
13
14/*
15 * Boot Device : one of
16 * spi/sd/nand/onenand, qspi/nor
17 */
18
19BOOT_FROM	sd
20
21/*
22 * Device Configuration Data (DCD)
23 *
24 * Each entry must have the format:
25 * Addr-type           Address        Value
26 *
27 * where:
28 *	Addr-type register length (1,2 or 4 bytes)
29 *	Address	  absolute address of the register
30 *	value	  value to be stored in the register
31 */
32
33/* Enable all clocks */
34DATA 4 0x020c4068 0xffffffff
35DATA 4 0x020c406c 0xffffffff
36DATA 4 0x020c4070 0xffffffff
37DATA 4 0x020c4074 0xffffffff
38DATA 4 0x020c4078 0xffffffff
39DATA 4 0x020c407c 0xffffffff
40DATA 4 0x020c4080 0xffffffff
41DATA 4 0x020c4084 0xffffffff
42
43/* IOMUX - DDR IO Type */
44DATA 4 0x020e0618 0x000c0000
45DATA 4 0x020e05fc 0x00000000
46
47/* Clock */
48DATA 4 0x020e032c 0x00000030
49
50/* Address */
51DATA 4 0x020e0300 0x00000020
52DATA 4 0x020e02fc 0x00000020
53DATA 4 0x020e05f4 0x00000020
54
55/* Control */
56DATA 4 0x020e0340 0x00000020
57
58DATA 4 0x020e0320 0x00000000
59DATA 4 0x020e0310 0x00000020
60DATA 4 0x020e0314 0x00000020
61DATA 4 0x020e0614 0x00000020
62
63/* Data Strobe */
64DATA 4 0x020e05f8 0x00020000
65DATA 4 0x020e0330 0x00000028
66DATA 4 0x020e0334 0x00000028
67DATA 4 0x020e0338 0x00000028
68DATA 4 0x020e033c 0x00000028
69
70/* Data */
71DATA 4 0x020e0608 0x00020000
72DATA 4 0x020e060c 0x00000028
73DATA 4 0x020e0610 0x00000028
74DATA 4 0x020e061c 0x00000028
75DATA 4 0x020e0620 0x00000028
76DATA 4 0x020e02ec 0x00000028
77DATA 4 0x020e02f0 0x00000028
78DATA 4 0x020e02f4 0x00000028
79DATA 4 0x020e02f8 0x00000028
80
81/* Calibrations - ZQ */
82DATA 4 0x021b0800 0xa1390003
83
84/* Write leveling */
85DATA 4 0x021b080c 0x00290025
86DATA 4 0x021b0810 0x00220022
87
88/* DQS Read Gate */
89DATA 4 0x021b083c 0x41480144
90DATA 4 0x021b0840 0x01340130
91
92/* Read/Write Delay */
93DATA 4 0x021b0848 0x3C3E4244
94DATA 4 0x021b0850 0x34363638
95
96/* Read data bit delay */
97DATA 4 0x021b081c 0x33333333
98DATA 4 0x021b0820 0x33333333
99DATA 4 0x021b0824 0x33333333
100DATA 4 0x021b0828 0x33333333
101
102/* Complete calibration by forced measurement */
103DATA 4 0x021b08b8 0x00000800
104
105/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
106DATA 4 0x021b0004 0x0002002d
107DATA 4 0x021b0008 0x00333030
108DATA 4 0x021b000c 0x676b52f3
109DATA 4 0x021b0010 0xb66d8b63
110DATA 4 0x021b0014 0x01ff00db
111DATA 4 0x021b0018 0x00011740
112DATA 4 0x021b001c 0x00008000
113DATA 4 0x021b002c 0x000026d2
114DATA 4 0x021b0030 0x006b1023
115DATA 4 0x021b0040 0x0000005f
116DATA 4 0x021b0000 0x84190000
117
118/* Initialize MT41K256M16HA-125 - MR2 */
119DATA 4 0x021b001c 0x04008032
120/* MR3 */
121DATA 4 0x021b001c 0x00008033
122/* MR1 */
123DATA 4 0x021b001c 0x00048031
124/* MR0 */
125DATA 4 0x021b001c 0x05208030
126/* DDR device ZQ calibration */
127DATA 4 0x021b001c 0x04008040
128
129/* Final DDR setup, before operation start */
130DATA 4 0x021b0020 0x00000800
131DATA 4 0x021b0818 0x00011117
132DATA 4 0x021b001c 0x00000000
133