1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 */ 5 6#define __ASSEMBLY__ 7#include <config.h> 8 9/* image version */ 10 11IMAGE_VERSION 2 12 13/* 14 * Boot Device : one of 15 * spi/sd/nand/onenand, qspi/nor 16 */ 17 18BOOT_FROM sd 19 20/* 21 * Device Configuration Data (DCD) 22 * 23 * Each entry must have the format: 24 * Addr-type Address Value 25 * 26 * where: 27 * Addr-type register length (1,2 or 4 bytes) 28 * Address absolute address of the register 29 * value value to be stored in the register 30 */ 31 32/* Enable all clocks */ 33DATA 4 0x020c4068 0xffffffff 34DATA 4 0x020c406c 0xffffffff 35DATA 4 0x020c4070 0xffffffff 36DATA 4 0x020c4074 0xffffffff 37DATA 4 0x020c4078 0xffffffff 38DATA 4 0x020c407c 0xffffffff 39DATA 4 0x020c4080 0xffffffff 40DATA 4 0x020c4084 0xffffffff 41 42/* IOMUX - DDR IO Type */ 43DATA 4 0x020e0618 0x000c0000 44DATA 4 0x020e05fc 0x00000000 45 46/* Clock */ 47DATA 4 0x020e032c 0x00000030 48 49/* Address */ 50DATA 4 0x020e0300 0x00000030 51DATA 4 0x020e02fc 0x00000030 52DATA 4 0x020e05f4 0x00000030 53 54/* Control */ 55DATA 4 0x020e0340 0x00000030 56 57DATA 4 0x020e0320 0x00000000 58DATA 4 0x020e0310 0x00000030 59DATA 4 0x020e0314 0x00000030 60DATA 4 0x020e0614 0x00000030 61 62/* Data Strobe */ 63DATA 4 0x020e05f8 0x00020000 64DATA 4 0x020e0330 0x00000030 65DATA 4 0x020e0334 0x00000030 66DATA 4 0x020e0338 0x00000030 67DATA 4 0x020e033c 0x00000030 68 69/* Data */ 70DATA 4 0x020e0608 0x00020000 71DATA 4 0x020e060c 0x00000030 72DATA 4 0x020e0610 0x00000030 73DATA 4 0x020e061c 0x00000030 74DATA 4 0x020e0620 0x00000030 75DATA 4 0x020e02ec 0x00000030 76DATA 4 0x020e02f0 0x00000030 77DATA 4 0x020e02f4 0x00000030 78DATA 4 0x020e02f8 0x00000030 79 80/* Calibrations - ZQ */ 81DATA 4 0x021b0800 0xa1390003 82 83/* Write leveling */ 84DATA 4 0x021b080c 0x002C003D 85DATA 4 0x021b0810 0x00110046 86 87/* DQS Read Gate */ 88DATA 4 0x021b083c 0x4160016C 89DATA 4 0x021b0840 0x013C016C 90 91/* Read/Write Delay */ 92DATA 4 0x021b0848 0x46424446 93DATA 4 0x021b0850 0x3A3C3C3A 94 95DATA 4 0x021b08c0 0x2492244A 96 97/* read data bit delay */ 98DATA 4 0x021b081c 0x33333333 99DATA 4 0x021b0820 0x33333333 100DATA 4 0x021b0824 0x33333333 101DATA 4 0x021b0828 0x33333333 102 103/* Complete calibration by forced measurement */ 104DATA 4 0x021b08b8 0x00000800 105 106/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 107DATA 4 0x021b0004 0x0002002d 108DATA 4 0x021b0008 0x00333030 109DATA 4 0x021b000c 0x676b52f3 110DATA 4 0x021b0010 0xb66d8b63 111DATA 4 0x021b0014 0x01ff00db 112DATA 4 0x021b0018 0x00011740 113DATA 4 0x021b001c 0x00008000 114DATA 4 0x021b002c 0x000026d2 115DATA 4 0x021b0030 0x006b1023 116DATA 4 0x021b0040 0x0000007f 117DATA 4 0x021b0000 0x85190000 118 119/* Initialize MT41K256M16HA-125 - MR2 */ 120DATA 4 0x021b001c 0x04008032 121/* MR3 */ 122DATA 4 0x021b001c 0x00008033 123/* MR1 */ 124DATA 4 0x021b001c 0x00068031 125/* MR0 */ 126DATA 4 0x021b001c 0x05208030 127/* DDR device ZQ calibration */ 128DATA 4 0x021b001c 0x04008040 129 130/* Final DDR setup, before operation start */ 131DATA 4 0x021b0020 0x00000800 132DATA 4 0x021b0818 0x00022227 133DATA 4 0x021b0004 0x0002556d 134DATA 4 0x021b0404 0x00011006 135DATA 4 0x021b001c 0x00000000 136