1 /*
2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/gpio.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/io.h>
17 #include <common.h>
18 #include <linux/sizes.h>
19 #include <mmc.h>
20 #include <power/pmic.h>
21 #include <power/pfuze100_pmic.h>
22 #include "../common/pfuze.h"
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
27 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
28 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
29 
30 int dram_init(void)
31 {
32 	gd->ram_size = imx_ddr_size();
33 
34 	return 0;
35 }
36 
37 static iomux_v3_cfg_t const uart1_pads[] = {
38 	MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 	MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 };
41 
42 static iomux_v3_cfg_t const wdog_pads[] = {
43 	MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
44 };
45 
46 static void setup_iomux_uart(void)
47 {
48 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
49 }
50 
51 #ifdef CONFIG_DM_PMIC_PFUZE100
52 int power_init_board(void)
53 {
54 	struct udevice *dev;
55 	int ret;
56 	u32 dev_id, rev_id, i;
57 	u32 switch_num = 6;
58 	u32 offset = PFUZE100_SW1CMODE;
59 
60 	ret = pmic_get("pfuze100", &dev);
61 	if (ret == -ENODEV)
62 		return 0;
63 
64 	if (ret != 0)
65 		return ret;
66 
67 	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
68 	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
69 	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
70 
71 
72 	/* Init mode to APS_PFM */
73 	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
74 
75 	for (i = 0; i < switch_num - 1; i++)
76 		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
77 
78 	/* set SW1AB staby volatage 0.975V */
79 	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
80 
81 	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
82 	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
83 
84 	/* set SW1C staby volatage 0.975V */
85 	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
86 
87 	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
88 	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
89 
90 	return 0;
91 }
92 #endif
93 
94 int board_early_init_f(void)
95 {
96 	setup_iomux_uart();
97 
98 	return 0;
99 }
100 
101 int board_init(void)
102 {
103 	/* Address of boot parameters */
104 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
105 
106 	return 0;
107 }
108 
109 int board_late_init(void)
110 {
111 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
112 
113 	return 0;
114 }
115 
116 int checkboard(void)
117 {
118 	puts("Board: MX6SLL EVK\n");
119 
120 	return 0;
121 }
122 
123 int board_mmc_get_env_dev(int devno)
124 {
125 	return devno;
126 }
127 
128 int mmc_map_to_kernel_blk(int devno)
129 {
130 	return devno;
131 }
132