1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/iomux.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/spi.h> 17 #include <asm/io.h> 18 #include <linux/sizes.h> 19 #include <common.h> 20 #include <fsl_esdhc.h> 21 #include <mmc.h> 22 #include <netdev.h> 23 #include <usb.h> 24 #include <usb/ehci-fsl.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 29 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 30 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31 32 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ 33 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 34 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 35 36 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 38 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 39 40 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 42 43 #define ETH_PHY_RESET IMX_GPIO_NR(4, 21) 44 45 int dram_init(void) 46 { 47 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 48 49 return 0; 50 } 51 52 static iomux_v3_cfg_t const uart1_pads[] = { 53 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 54 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 55 }; 56 57 static iomux_v3_cfg_t const usdhc1_pads[] = { 58 /* 8 bit SD */ 59 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 62 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 63 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 64 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 70 /*CD pin*/ 71 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 72 }; 73 74 static iomux_v3_cfg_t const usdhc2_pads[] = { 75 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 82 /*CD pin*/ 83 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), 84 }; 85 86 static iomux_v3_cfg_t const usdhc3_pads[] = { 87 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 94 /*CD pin*/ 95 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), 96 }; 97 98 static iomux_v3_cfg_t const fec_pads[] = { 99 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 100 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 107 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), 108 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), 109 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 110 }; 111 112 #ifdef CONFIG_MXC_SPI 113 static iomux_v3_cfg_t ecspi1_pads[] = { 114 MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 115 MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 116 MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 117 MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 118 }; 119 120 int board_spi_cs_gpio(unsigned bus, unsigned cs) 121 { 122 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; 123 } 124 125 static void setup_spi(void) 126 { 127 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 128 } 129 #endif 130 131 static void setup_iomux_uart(void) 132 { 133 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 134 } 135 136 static void setup_iomux_fec(void) 137 { 138 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 139 140 /* Reset LAN8720 PHY */ 141 gpio_direction_output(ETH_PHY_RESET , 0); 142 udelay(1000); 143 gpio_set_value(ETH_PHY_RESET, 1); 144 } 145 146 #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) 147 #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) 148 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) 149 150 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 151 {USDHC1_BASE_ADDR}, 152 {USDHC2_BASE_ADDR, 0, 4}, 153 {USDHC3_BASE_ADDR, 0, 4}, 154 }; 155 156 int board_mmc_getcd(struct mmc *mmc) 157 { 158 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 159 int ret = 0; 160 161 switch (cfg->esdhc_base) { 162 case USDHC1_BASE_ADDR: 163 ret = !gpio_get_value(USDHC1_CD_GPIO); 164 break; 165 case USDHC2_BASE_ADDR: 166 ret = !gpio_get_value(USDHC2_CD_GPIO); 167 break; 168 case USDHC3_BASE_ADDR: 169 ret = !gpio_get_value(USDHC3_CD_GPIO); 170 break; 171 } 172 173 return ret; 174 } 175 176 int board_mmc_init(bd_t *bis) 177 { 178 int i, ret; 179 180 /* 181 * According to the board_mmc_init() the following map is done: 182 * (U-boot device node) (Physical Port) 183 * mmc0 USDHC1 184 * mmc1 USDHC2 185 * mmc2 USDHC3 186 */ 187 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 188 switch (i) { 189 case 0: 190 imx_iomux_v3_setup_multiple_pads( 191 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 192 gpio_direction_input(USDHC1_CD_GPIO); 193 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 194 break; 195 case 1: 196 imx_iomux_v3_setup_multiple_pads( 197 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 198 gpio_direction_input(USDHC2_CD_GPIO); 199 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 200 break; 201 case 2: 202 imx_iomux_v3_setup_multiple_pads( 203 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 204 gpio_direction_input(USDHC3_CD_GPIO); 205 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 206 break; 207 default: 208 printf("Warning: you configured more USDHC controllers" 209 "(%d) than supported by the board\n", i + 1); 210 return -EINVAL; 211 } 212 213 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 214 if (ret) { 215 printf("Warning: failed to initialize " 216 "mmc dev %d\n", i); 217 return ret; 218 } 219 } 220 221 return 0; 222 } 223 224 #ifdef CONFIG_FEC_MXC 225 int board_eth_init(bd_t *bis) 226 { 227 setup_iomux_fec(); 228 229 return cpu_eth_init(bis); 230 } 231 232 static int setup_fec(void) 233 { 234 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 235 236 /* clear gpr1[14], gpr1[18:17] to select anatop clock */ 237 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); 238 239 return enable_fec_anatop_clock(ENET_50MHZ); 240 } 241 #endif 242 243 #ifdef CONFIG_USB_EHCI_MX6 244 #define USB_OTHERREGS_OFFSET 0x800 245 #define UCTRL_PWR_POL (1 << 9) 246 247 static iomux_v3_cfg_t const usb_otg_pads[] = { 248 /* OTG1 */ 249 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 250 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 251 /* OTG2 */ 252 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) 253 }; 254 255 static void setup_usb(void) 256 { 257 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 258 ARRAY_SIZE(usb_otg_pads)); 259 } 260 261 int board_usb_phy_mode(int port) 262 { 263 if (port == 1) 264 return USB_INIT_HOST; 265 else 266 return usb_phy_mode(port); 267 } 268 269 int board_ehci_hcd_init(int port) 270 { 271 u32 *usbnc_usb_ctrl; 272 273 if (port > 1) 274 return -EINVAL; 275 276 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 277 port * 4); 278 279 /* Set Power polarity */ 280 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 281 282 return 0; 283 } 284 #endif 285 286 int board_early_init_f(void) 287 { 288 setup_iomux_uart(); 289 #ifdef CONFIG_MXC_SPI 290 setup_spi(); 291 #endif 292 return 0; 293 } 294 295 int board_init(void) 296 { 297 /* address of boot parameters */ 298 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 299 300 #ifdef CONFIG_FEC_MXC 301 setup_fec(); 302 #endif 303 304 #ifdef CONFIG_USB_EHCI_MX6 305 setup_usb(); 306 #endif 307 308 return 0; 309 } 310 311 int checkboard(void) 312 { 313 puts("Board: MX6SLEVK\n"); 314 315 return 0; 316 } 317