1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/iomux.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/iomux-v3.h> 18 #include <asm/imx-common/mxc_i2c.h> 19 #include <asm/imx-common/spi.h> 20 #include <asm/io.h> 21 #include <linux/sizes.h> 22 #include <common.h> 23 #include <fsl_esdhc.h> 24 #include <i2c.h> 25 #include <mmc.h> 26 #include <netdev.h> 27 #include <power/pmic.h> 28 #include <power/pfuze100_pmic.h> 29 #include "../common/pfuze.h" 30 #include <usb.h> 31 #include <usb/ehci-ci.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ 40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 45 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 46 47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 49 50 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 51 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ 52 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ 53 PAD_CTL_SRE_FAST) 54 55 #define ETH_PHY_POWER IMX_GPIO_NR(4, 21) 56 57 int dram_init(void) 58 { 59 gd->ram_size = imx_ddr_size(); 60 61 return 0; 62 } 63 64 static iomux_v3_cfg_t const uart1_pads[] = { 65 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 66 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 67 }; 68 69 static iomux_v3_cfg_t const usdhc1_pads[] = { 70 /* 8 bit SD */ 71 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 82 /*CD pin*/ 83 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 84 }; 85 86 static iomux_v3_cfg_t const usdhc2_pads[] = { 87 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 94 /*CD pin*/ 95 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), 96 }; 97 98 static iomux_v3_cfg_t const usdhc3_pads[] = { 99 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 106 /*CD pin*/ 107 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), 108 }; 109 110 static iomux_v3_cfg_t const fec_pads[] = { 111 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 112 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 113 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), 114 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 115 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 116 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 117 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 118 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 119 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), 120 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), 121 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 122 }; 123 124 #ifdef CONFIG_MXC_SPI 125 static iomux_v3_cfg_t ecspi1_pads[] = { 126 MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 127 MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 128 MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 129 MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 130 }; 131 132 int board_spi_cs_gpio(unsigned bus, unsigned cs) 133 { 134 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; 135 } 136 137 static void setup_spi(void) 138 { 139 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 140 } 141 #endif 142 143 static void setup_iomux_uart(void) 144 { 145 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 146 } 147 148 static void setup_iomux_fec(void) 149 { 150 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 151 152 /* Power up LAN8720 PHY */ 153 gpio_request(ETH_PHY_POWER, "eth_pwr"); 154 gpio_direction_output(ETH_PHY_POWER , 1); 155 udelay(15000); 156 } 157 158 int board_mmc_get_env_dev(int devno) 159 { 160 return devno; 161 } 162 163 #ifdef CONFIG_DM_PMIC_PFUZE100 164 int power_init_board(void) 165 { 166 struct udevice *dev; 167 int ret; 168 u32 dev_id, rev_id, i; 169 u32 switch_num = 6; 170 u32 offset = PFUZE100_SW1CMODE; 171 172 ret = pmic_get("pfuze100", &dev); 173 if (ret == -ENODEV) 174 return 0; 175 176 if (ret != 0) 177 return ret; 178 179 dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); 180 rev_id = pmic_reg_read(dev, PFUZE100_REVID); 181 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); 182 183 /* set SW1AB staby volatage 0.975V */ 184 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); 185 186 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 187 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); 188 189 /* set SW1C staby volatage 0.975V */ 190 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); 191 192 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 193 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); 194 195 /* Init mode to APS_PFM */ 196 pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); 197 198 for (i = 0; i < switch_num - 1; i++) 199 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); 200 201 return 0; 202 } 203 #endif 204 205 #ifdef CONFIG_FEC_MXC 206 int board_eth_init(bd_t *bis) 207 { 208 setup_iomux_fec(); 209 210 return cpu_eth_init(bis); 211 } 212 213 static int setup_fec(void) 214 { 215 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 216 217 /* clear gpr1[14], gpr1[18:17] to select anatop clock */ 218 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); 219 220 return enable_fec_anatop_clock(0, ENET_50MHZ); 221 } 222 #endif 223 224 #ifdef CONFIG_USB_EHCI_MX6 225 #define USB_OTHERREGS_OFFSET 0x800 226 #define UCTRL_PWR_POL (1 << 9) 227 228 static iomux_v3_cfg_t const usb_otg_pads[] = { 229 /* OTG1 */ 230 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 231 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), 232 /* OTG2 */ 233 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) 234 }; 235 236 static void setup_usb(void) 237 { 238 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 239 ARRAY_SIZE(usb_otg_pads)); 240 } 241 242 int board_usb_phy_mode(int port) 243 { 244 if (port == 1) 245 return USB_INIT_HOST; 246 else 247 return usb_phy_mode(port); 248 } 249 250 int board_ehci_hcd_init(int port) 251 { 252 u32 *usbnc_usb_ctrl; 253 254 if (port > 1) 255 return -EINVAL; 256 257 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 258 port * 4); 259 260 /* Set Power polarity */ 261 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 262 263 return 0; 264 } 265 #endif 266 267 int board_early_init_f(void) 268 { 269 setup_iomux_uart(); 270 271 return 0; 272 } 273 274 int board_init(void) 275 { 276 /* address of boot parameters */ 277 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 278 279 #ifdef CONFIG_MXC_SPI 280 gpio_request(IMX_GPIO_NR(4, 11), "spi_cs"); 281 setup_spi(); 282 #endif 283 284 #ifdef CONFIG_FEC_MXC 285 setup_fec(); 286 #endif 287 288 #ifdef CONFIG_USB_EHCI_MX6 289 setup_usb(); 290 #endif 291 292 return 0; 293 } 294 295 int checkboard(void) 296 { 297 puts("Board: MX6SLEVK\n"); 298 299 return 0; 300 } 301 302 #ifdef CONFIG_SPL_BUILD 303 #include <spl.h> 304 #include <libfdt.h> 305 306 #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) 307 #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) 308 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) 309 310 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 311 {USDHC1_BASE_ADDR}, 312 {USDHC2_BASE_ADDR, 0, 4}, 313 {USDHC3_BASE_ADDR, 0, 4}, 314 }; 315 316 int board_mmc_getcd(struct mmc *mmc) 317 { 318 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 319 int ret = 0; 320 321 switch (cfg->esdhc_base) { 322 case USDHC1_BASE_ADDR: 323 ret = !gpio_get_value(USDHC1_CD_GPIO); 324 break; 325 case USDHC2_BASE_ADDR: 326 ret = !gpio_get_value(USDHC2_CD_GPIO); 327 break; 328 case USDHC3_BASE_ADDR: 329 ret = !gpio_get_value(USDHC3_CD_GPIO); 330 break; 331 } 332 333 return ret; 334 } 335 336 int board_mmc_init(bd_t *bis) 337 { 338 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 339 u32 val; 340 u32 port; 341 342 val = readl(&src_regs->sbmr1); 343 344 /* Boot from USDHC */ 345 port = (val >> 11) & 0x3; 346 switch (port) { 347 case 0: 348 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, 349 ARRAY_SIZE(usdhc1_pads)); 350 gpio_direction_input(USDHC1_CD_GPIO); 351 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; 352 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 353 break; 354 case 1: 355 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, 356 ARRAY_SIZE(usdhc2_pads)); 357 gpio_direction_input(USDHC2_CD_GPIO); 358 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 359 usdhc_cfg[0].max_bus_width = 4; 360 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 361 break; 362 case 2: 363 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, 364 ARRAY_SIZE(usdhc3_pads)); 365 gpio_direction_input(USDHC3_CD_GPIO); 366 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 367 usdhc_cfg[0].max_bus_width = 4; 368 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 369 break; 370 } 371 372 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 373 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 374 } 375 376 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = { 377 .dram_sdqs0 = 0x00003030, 378 .dram_sdqs1 = 0x00003030, 379 .dram_sdqs2 = 0x00003030, 380 .dram_sdqs3 = 0x00003030, 381 .dram_dqm0 = 0x00000030, 382 .dram_dqm1 = 0x00000030, 383 .dram_dqm2 = 0x00000030, 384 .dram_dqm3 = 0x00000030, 385 .dram_cas = 0x00000030, 386 .dram_ras = 0x00000030, 387 .dram_sdclk_0 = 0x00000028, 388 .dram_reset = 0x00000030, 389 .dram_sdba2 = 0x00000000, 390 .dram_odt0 = 0x00000008, 391 .dram_odt1 = 0x00000008, 392 }; 393 394 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = { 395 .grp_b0ds = 0x00000030, 396 .grp_b1ds = 0x00000030, 397 .grp_b2ds = 0x00000030, 398 .grp_b3ds = 0x00000030, 399 .grp_addds = 0x00000030, 400 .grp_ctlds = 0x00000030, 401 .grp_ddrmode_ctl = 0x00020000, 402 .grp_ddrpke = 0x00000000, 403 .grp_ddrmode = 0x00020000, 404 .grp_ddr_type = 0x00080000, 405 }; 406 407 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 408 .p0_mpdgctrl0 = 0x20000000, 409 .p0_mpdgctrl1 = 0x00000000, 410 .p0_mprddlctl = 0x4241444a, 411 .p0_mpwrdlctl = 0x3030312b, 412 .mpzqlp2ctl = 0x1b4700c7, 413 }; 414 415 static struct mx6_lpddr2_cfg mem_ddr = { 416 .mem_speed = 800, 417 .density = 4, 418 .width = 32, 419 .banks = 8, 420 .rowaddr = 14, 421 .coladdr = 10, 422 .trcd_lp = 2000, 423 .trppb_lp = 2000, 424 .trpab_lp = 2250, 425 .trasmin = 4200, 426 }; 427 428 static void ccgr_init(void) 429 { 430 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 431 432 writel(0xFFFFFFFF, &ccm->CCGR0); 433 writel(0xFFFFFFFF, &ccm->CCGR1); 434 writel(0xFFFFFFFF, &ccm->CCGR2); 435 writel(0xFFFFFFFF, &ccm->CCGR3); 436 writel(0xFFFFFFFF, &ccm->CCGR4); 437 writel(0xFFFFFFFF, &ccm->CCGR5); 438 writel(0xFFFFFFFF, &ccm->CCGR6); 439 440 writel(0x00260324, &ccm->cbcmr); 441 } 442 443 static void spl_dram_init(void) 444 { 445 struct mx6_ddr_sysinfo sysinfo = { 446 .dsize = mem_ddr.width / 32, 447 .cs_density = 20, 448 .ncs = 2, 449 .cs1_mirror = 0, 450 .walat = 0, 451 .ralat = 2, 452 .mif3_mode = 3, 453 .bi_on = 1, 454 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ 455 .rtt_nom = 0, 456 .sde_to_rst = 0, /* LPDDR2 does not need this field */ 457 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ 458 .ddr_type = DDR_TYPE_LPDDR2, 459 .refsel = 0, /* Refresh cycles at 64KHz */ 460 .refr = 3, /* 4 refresh commands per refresh cycle */ 461 }; 462 mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); 463 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 464 } 465 466 void board_init_f(ulong dummy) 467 { 468 /* setup AIPS and disable watchdog */ 469 arch_cpu_init(); 470 471 ccgr_init(); 472 473 /* iomux and setup of i2c */ 474 board_early_init_f(); 475 476 /* setup GP timer */ 477 timer_init(); 478 479 /* UART clocks enabled and gd valid - init serial console */ 480 preloader_console_init(); 481 482 /* DDR initialization */ 483 spl_dram_init(); 484 485 /* Clear the BSS. */ 486 memset(__bss_start, 0, __bss_end - __bss_start); 487 488 /* load/boot image from boot device */ 489 board_init_r(NULL, 0); 490 } 491 #endif 492