1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/iomux.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/spi.h> 17 #include <asm/io.h> 18 #include <linux/sizes.h> 19 #include <common.h> 20 #include <fsl_esdhc.h> 21 #include <mmc.h> 22 #include <netdev.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 27 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 28 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 30 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ 31 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 32 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 33 34 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 37 38 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 39 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 40 41 #define ETH_PHY_RESET IMX_GPIO_NR(4, 21) 42 43 int dram_init(void) 44 { 45 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 46 47 return 0; 48 } 49 50 static iomux_v3_cfg_t const uart1_pads[] = { 51 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 52 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 53 }; 54 55 static iomux_v3_cfg_t const usdhc1_pads[] = { 56 /* 8 bit SD */ 57 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 58 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 59 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 62 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 63 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 64 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 68 /*CD pin*/ 69 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 70 }; 71 72 static iomux_v3_cfg_t const usdhc2_pads[] = { 73 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 80 /*CD pin*/ 81 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), 82 }; 83 84 static iomux_v3_cfg_t const usdhc3_pads[] = { 85 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 92 /*CD pin*/ 93 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), 94 }; 95 96 static iomux_v3_cfg_t const fec_pads[] = { 97 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 98 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 99 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), 100 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), 107 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 108 }; 109 110 #ifdef CONFIG_MXC_SPI 111 static iomux_v3_cfg_t ecspi1_pads[] = { 112 MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 113 MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 114 MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 115 MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 116 }; 117 118 int board_spi_cs_gpio(unsigned bus, unsigned cs) 119 { 120 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; 121 } 122 123 static void setup_spi(void) 124 { 125 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 126 } 127 #endif 128 129 static void setup_iomux_uart(void) 130 { 131 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 132 } 133 134 static void setup_iomux_fec(void) 135 { 136 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 137 138 /* Reset LAN8720 PHY */ 139 gpio_direction_output(ETH_PHY_RESET , 0); 140 udelay(1000); 141 gpio_set_value(ETH_PHY_RESET, 1); 142 } 143 144 #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) 145 #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) 146 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) 147 148 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 149 {USDHC1_BASE_ADDR}, 150 {USDHC2_BASE_ADDR, 0, 4}, 151 {USDHC3_BASE_ADDR, 0, 4}, 152 }; 153 154 int board_mmc_getcd(struct mmc *mmc) 155 { 156 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 157 int ret = 0; 158 159 switch (cfg->esdhc_base) { 160 case USDHC1_BASE_ADDR: 161 ret = !gpio_get_value(USDHC1_CD_GPIO); 162 break; 163 case USDHC2_BASE_ADDR: 164 ret = !gpio_get_value(USDHC2_CD_GPIO); 165 break; 166 case USDHC3_BASE_ADDR: 167 ret = !gpio_get_value(USDHC3_CD_GPIO); 168 break; 169 } 170 171 return ret; 172 } 173 174 int board_mmc_init(bd_t *bis) 175 { 176 int i, ret; 177 178 /* 179 * According to the board_mmc_init() the following map is done: 180 * (U-boot device node) (Physical Port) 181 * mmc0 USDHC1 182 * mmc1 USDHC2 183 * mmc2 USDHC3 184 */ 185 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 186 switch (i) { 187 case 0: 188 imx_iomux_v3_setup_multiple_pads( 189 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 190 gpio_direction_input(USDHC1_CD_GPIO); 191 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 192 break; 193 case 1: 194 imx_iomux_v3_setup_multiple_pads( 195 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 196 gpio_direction_input(USDHC2_CD_GPIO); 197 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 198 break; 199 case 2: 200 imx_iomux_v3_setup_multiple_pads( 201 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 202 gpio_direction_input(USDHC3_CD_GPIO); 203 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 204 break; 205 default: 206 printf("Warning: you configured more USDHC controllers" 207 "(%d) than supported by the board\n", i + 1); 208 return -EINVAL; 209 } 210 211 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 212 if (ret) { 213 printf("Warning: failed to initialize " 214 "mmc dev %d\n", i); 215 return ret; 216 } 217 } 218 219 return 0; 220 } 221 222 #ifdef CONFIG_FEC_MXC 223 int board_eth_init(bd_t *bis) 224 { 225 setup_iomux_fec(); 226 227 return cpu_eth_init(bis); 228 } 229 230 static int setup_fec(void) 231 { 232 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 233 234 /* clear gpr1[14], gpr1[18:17] to select anatop clock */ 235 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); 236 237 return enable_fec_anatop_clock(ENET_50MHz); 238 } 239 #endif 240 241 242 int board_early_init_f(void) 243 { 244 setup_iomux_uart(); 245 #ifdef CONFIG_MXC_SPI 246 setup_spi(); 247 #endif 248 return 0; 249 } 250 251 int board_init(void) 252 { 253 /* address of boot parameters */ 254 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 255 256 #ifdef CONFIG_FEC_MXC 257 setup_fec(); 258 #endif 259 return 0; 260 } 261 262 u32 get_board_rev(void) 263 { 264 return get_cpu_rev(); 265 } 266 267 int checkboard(void) 268 { 269 puts("Board: MX6SLEVK\n"); 270 271 return 0; 272 } 273