1 /*
2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/io.h>
21 #include <linux/sizes.h>
22 #include <common.h>
23 #include <fsl_esdhc.h>
24 #include <i2c.h>
25 #include <mmc.h>
26 #include <netdev.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
29 #include "../common/pfuze.h"
30 #include <usb.h>
31 #include <usb/ehci-fsl.h>
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
36 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
37 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
38 
39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
40 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
41 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
42 
43 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
44 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
45 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
46 
47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
48 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
49 
50 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
51 		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
52 		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
53 		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54 
55 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
56 			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
57 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
58 			PAD_CTL_SRE_FAST)
59 
60 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
61 
62 int dram_init(void)
63 {
64 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
65 
66 	return 0;
67 }
68 
69 static iomux_v3_cfg_t const uart1_pads[] = {
70 	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
71 	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
72 };
73 
74 static iomux_v3_cfg_t const usdhc1_pads[] = {
75 	/* 8 bit SD */
76 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 	MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 	MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 	MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 	MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 
87 	/*CD pin*/
88 	MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
89 };
90 
91 static iomux_v3_cfg_t const usdhc2_pads[] = {
92 	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 
99 	/*CD pin*/
100 	MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
101 };
102 
103 static iomux_v3_cfg_t const usdhc3_pads[] = {
104 	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 
111 	/*CD pin*/
112 	MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 };
114 
115 static iomux_v3_cfg_t const fec_pads[] = {
116 	MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 	MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 	MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 	MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 	MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 	MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 	MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 	MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 	MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
126 	MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 };
128 
129 #ifdef CONFIG_MXC_SPI
130 static iomux_v3_cfg_t ecspi1_pads[] = {
131 	MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
132 	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
133 	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
134 	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
135 };
136 
137 int board_spi_cs_gpio(unsigned bus, unsigned cs)
138 {
139 	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
140 }
141 
142 static void setup_spi(void)
143 {
144 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
145 }
146 #endif
147 
148 static void setup_iomux_uart(void)
149 {
150 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
151 }
152 
153 static void setup_iomux_fec(void)
154 {
155 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
156 
157 	/* Reset LAN8720 PHY */
158 	gpio_direction_output(ETH_PHY_RESET , 0);
159 	udelay(1000);
160 	gpio_set_value(ETH_PHY_RESET, 1);
161 }
162 
163 #define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
164 #define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
165 #define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
166 
167 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
168 	{USDHC1_BASE_ADDR},
169 	{USDHC2_BASE_ADDR, 0, 4},
170 	{USDHC3_BASE_ADDR, 0, 4},
171 };
172 
173 int board_mmc_getcd(struct mmc *mmc)
174 {
175 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
176 	int ret = 0;
177 
178 	switch (cfg->esdhc_base) {
179 	case USDHC1_BASE_ADDR:
180 		ret = !gpio_get_value(USDHC1_CD_GPIO);
181 		break;
182 	case USDHC2_BASE_ADDR:
183 		ret = !gpio_get_value(USDHC2_CD_GPIO);
184 		break;
185 	case USDHC3_BASE_ADDR:
186 		ret = !gpio_get_value(USDHC3_CD_GPIO);
187 		break;
188 	}
189 
190 	return ret;
191 }
192 
193 int board_mmc_init(bd_t *bis)
194 {
195 #ifndef CONFIG_SPL_BUILD
196 	int i, ret;
197 
198 	/*
199 	 * According to the board_mmc_init() the following map is done:
200 	 * (U-boot device node)    (Physical Port)
201 	 * mmc0                    USDHC1
202 	 * mmc1                    USDHC2
203 	 * mmc2                    USDHC3
204 	 */
205 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
206 		switch (i) {
207 		case 0:
208 			imx_iomux_v3_setup_multiple_pads(
209 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
210 			gpio_direction_input(USDHC1_CD_GPIO);
211 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
212 			break;
213 		case 1:
214 			imx_iomux_v3_setup_multiple_pads(
215 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
216 			gpio_direction_input(USDHC2_CD_GPIO);
217 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
218 			break;
219 		case 2:
220 			imx_iomux_v3_setup_multiple_pads(
221 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
222 			gpio_direction_input(USDHC3_CD_GPIO);
223 			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
224 			break;
225 		default:
226 			printf("Warning: you configured more USDHC controllers"
227 				"(%d) than supported by the board\n", i + 1);
228 			return -EINVAL;
229 			}
230 
231 			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
232 			if (ret) {
233 				printf("Warning: failed to initialize "
234 					"mmc dev %d\n", i);
235 				return ret;
236 			}
237 	}
238 
239 	return 0;
240 #else
241 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
242 	u32 val;
243 	u32 port;
244 
245 	val = readl(&src_regs->sbmr1);
246 
247 	/* Boot from USDHC */
248 	port = (val >> 11) & 0x3;
249 	switch (port) {
250 	case 0:
251 		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
252 						 ARRAY_SIZE(usdhc1_pads));
253 		gpio_direction_input(USDHC1_CD_GPIO);
254 		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
255 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
256 		break;
257 	case 1:
258 		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
259 						 ARRAY_SIZE(usdhc2_pads));
260 		gpio_direction_input(USDHC2_CD_GPIO);
261 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
262 		usdhc_cfg[0].max_bus_width = 4;
263 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
264 		break;
265 	case 2:
266 		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
267 						 ARRAY_SIZE(usdhc3_pads));
268 		gpio_direction_input(USDHC3_CD_GPIO);
269 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
270 		usdhc_cfg[0].max_bus_width = 4;
271 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
272 		break;
273 	}
274 
275 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
276 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
277 #endif
278 }
279 
280 #ifdef CONFIG_SYS_I2C_MXC
281 #define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
282 /* I2C1 for PMIC */
283 struct i2c_pads_info i2c_pad_info1 = {
284 	.sda = {
285 		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
286 		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
287 		.gp = IMX_GPIO_NR(3, 13),
288 	},
289 	.scl = {
290 		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
291 		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
292 		.gp = IMX_GPIO_NR(3, 12),
293 	},
294 };
295 
296 int power_init_board(void)
297 {
298 	struct pmic *p;
299 
300 	p = pfuze_common_init(I2C_PMIC);
301 	if (!p)
302 		return -ENODEV;
303 
304 	return pfuze_mode_init(p, APS_PFM);
305 }
306 #endif
307 
308 #ifdef CONFIG_FEC_MXC
309 int board_eth_init(bd_t *bis)
310 {
311 	setup_iomux_fec();
312 
313 	return cpu_eth_init(bis);
314 }
315 
316 static int setup_fec(void)
317 {
318 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
319 
320 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
321 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
322 
323 	return enable_fec_anatop_clock(0, ENET_50MHZ);
324 }
325 #endif
326 
327 #ifdef CONFIG_USB_EHCI_MX6
328 #define USB_OTHERREGS_OFFSET	0x800
329 #define UCTRL_PWR_POL		(1 << 9)
330 
331 static iomux_v3_cfg_t const usb_otg_pads[] = {
332 	/* OTG1 */
333 	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
334 	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
335 	/* OTG2 */
336 	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
337 };
338 
339 static void setup_usb(void)
340 {
341 	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
342 					 ARRAY_SIZE(usb_otg_pads));
343 }
344 
345 int board_usb_phy_mode(int port)
346 {
347 	if (port == 1)
348 		return USB_INIT_HOST;
349 	else
350 		return usb_phy_mode(port);
351 }
352 
353 int board_ehci_hcd_init(int port)
354 {
355 	u32 *usbnc_usb_ctrl;
356 
357 	if (port > 1)
358 		return -EINVAL;
359 
360 	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
361 				 port * 4);
362 
363 	/* Set Power polarity */
364 	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
365 
366 	return 0;
367 }
368 #endif
369 
370 int board_early_init_f(void)
371 {
372 	setup_iomux_uart();
373 #ifdef CONFIG_MXC_SPI
374 	setup_spi();
375 #endif
376 	return 0;
377 }
378 
379 int board_init(void)
380 {
381 	/* address of boot parameters */
382 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
383 
384 #ifdef CONFIG_SYS_I2C_MXC
385 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
386 #endif
387 
388 #ifdef	CONFIG_FEC_MXC
389 	setup_fec();
390 #endif
391 
392 #ifdef CONFIG_USB_EHCI_MX6
393 	setup_usb();
394 #endif
395 
396 	return 0;
397 }
398 
399 int checkboard(void)
400 {
401 	puts("Board: MX6SLEVK\n");
402 
403 	return 0;
404 }
405 
406 #ifdef CONFIG_SPL_BUILD
407 #include <spl.h>
408 #include <libfdt.h>
409 
410 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
411 	.dram_sdqs0 = 0x00003030,
412 	.dram_sdqs1 = 0x00003030,
413 	.dram_sdqs2 = 0x00003030,
414 	.dram_sdqs3 = 0x00003030,
415 	.dram_dqm0 = 0x00000030,
416 	.dram_dqm1 = 0x00000030,
417 	.dram_dqm2 = 0x00000030,
418 	.dram_dqm3 = 0x00000030,
419 	.dram_cas  = 0x00000030,
420 	.dram_ras  = 0x00000030,
421 	.dram_sdclk_0 = 0x00000028,
422 	.dram_reset = 0x00000030,
423 	.dram_sdba2 = 0x00000000,
424 	.dram_odt0 = 0x00000008,
425 	.dram_odt1 = 0x00000008,
426 };
427 
428 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
429 	.grp_b0ds = 0x00000030,
430 	.grp_b1ds = 0x00000030,
431 	.grp_b2ds = 0x00000030,
432 	.grp_b3ds = 0x00000030,
433 	.grp_addds = 0x00000030,
434 	.grp_ctlds = 0x00000030,
435 	.grp_ddrmode_ctl = 0x00020000,
436 	.grp_ddrpke = 0x00000000,
437 	.grp_ddrmode = 0x00020000,
438 	.grp_ddr_type = 0x00080000,
439 };
440 
441 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
442 	.p0_mpdgctrl0 =  0x20000000,
443 	.p0_mpdgctrl1 =  0x00000000,
444 	.p0_mprddlctl =  0x4241444a,
445 	.p0_mpwrdlctl =  0x3030312b,
446 	.mpzqlp2ctl = 0x1b4700c7,
447 };
448 
449 static struct mx6_lpddr2_cfg mem_ddr = {
450 	.mem_speed = 800,
451 	.density = 4,
452 	.width = 32,
453 	.banks = 8,
454 	.rowaddr = 14,
455 	.coladdr = 10,
456 	.trcd_lp = 2000,
457 	.trppb_lp = 2000,
458 	.trpab_lp = 2250,
459 	.trasmin = 4200,
460 };
461 
462 static void ccgr_init(void)
463 {
464 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
465 
466 	writel(0xFFFFFFFF, &ccm->CCGR0);
467 	writel(0xFFFFFFFF, &ccm->CCGR1);
468 	writel(0xFFFFFFFF, &ccm->CCGR2);
469 	writel(0xFFFFFFFF, &ccm->CCGR3);
470 	writel(0xFFFFFFFF, &ccm->CCGR4);
471 	writel(0xFFFFFFFF, &ccm->CCGR5);
472 	writel(0xFFFFFFFF, &ccm->CCGR6);
473 
474 	writel(0x00260324, &ccm->cbcmr);
475 }
476 
477 static void spl_dram_init(void)
478 {
479 	struct mx6_ddr_sysinfo sysinfo = {
480 		.dsize = mem_ddr.width / 32,
481 		.cs_density = 20,
482 		.ncs = 2,
483 		.cs1_mirror = 0,
484 		.walat = 0,
485 		.ralat = 2,
486 		.mif3_mode = 3,
487 		.bi_on = 1,
488 		.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
489 		.rtt_nom = 0,
490 		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
491 		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
492 		.ddr_type = DDR_TYPE_LPDDR2,
493 	};
494 	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
495 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
496 }
497 
498 void board_init_f(ulong dummy)
499 {
500 	/* setup AIPS and disable watchdog */
501 	arch_cpu_init();
502 
503 	ccgr_init();
504 
505 	/* iomux and setup of i2c */
506 	board_early_init_f();
507 
508 	/* setup GP timer */
509 	timer_init();
510 
511 	/* UART clocks enabled and gd valid - init serial console */
512 	preloader_console_init();
513 
514 	/* DDR initialization */
515 	spl_dram_init();
516 
517 	/* Clear the BSS. */
518 	memset(__bss_start, 0, __bss_end - __bss_start);
519 
520 	/* load/boot image from boot device */
521 	board_init_r(NULL, 0);
522 }
523 
524 void reset_cpu(ulong addr)
525 {
526 }
527 #endif
528