1 /*
2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/spi.h>
20 #include <asm/io.h>
21 #include <linux/sizes.h>
22 #include <common.h>
23 #include <fsl_esdhc.h>
24 #include <i2c.h>
25 #include <mmc.h>
26 #include <netdev.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
29 #include "../common/pfuze.h"
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
34 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
35 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
36 
37 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
38 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
39 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
40 
41 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
42 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
43 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
44 
45 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
46 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
47 
48 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
49 			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
50 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
51 			PAD_CTL_SRE_FAST)
52 
53 #define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)
54 
55 int dram_init(void)
56 {
57 	gd->ram_size = imx_ddr_size();
58 
59 	return 0;
60 }
61 
62 static iomux_v3_cfg_t const uart1_pads[] = {
63 	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
64 	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
65 };
66 
67 #ifdef CONFIG_SPL_BUILD
68 static iomux_v3_cfg_t const usdhc1_pads[] = {
69 	/* 8 bit SD */
70 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 	MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 	MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 	MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 	MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 
81 	/*CD pin*/
82 	MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
83 };
84 
85 static iomux_v3_cfg_t const usdhc2_pads[] = {
86 	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 
93 	/*CD pin*/
94 	MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
95 };
96 
97 static iomux_v3_cfg_t const usdhc3_pads[] = {
98 	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 
105 	/*CD pin*/
106 	MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
107 };
108 #endif
109 
110 static iomux_v3_cfg_t const fec_pads[] = {
111 	MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 	MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
113 	MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 	MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 	MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 	MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 	MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 	MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 	MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
121 	MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
122 };
123 
124 #ifdef CONFIG_MXC_SPI
125 static iomux_v3_cfg_t ecspi1_pads[] = {
126 	MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
127 	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
128 	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
129 	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
130 };
131 
132 int board_spi_cs_gpio(unsigned bus, unsigned cs)
133 {
134 	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
135 }
136 
137 static void setup_spi(void)
138 {
139 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
140 }
141 #endif
142 
143 static void setup_iomux_uart(void)
144 {
145 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
146 }
147 
148 static void setup_iomux_fec(void)
149 {
150 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
151 
152 	/* Power up LAN8720 PHY */
153 	gpio_request(ETH_PHY_POWER, "eth_pwr");
154 	gpio_direction_output(ETH_PHY_POWER , 1);
155 	udelay(15000);
156 }
157 
158 int board_mmc_get_env_dev(int devno)
159 {
160 	return devno;
161 }
162 
163 #ifdef CONFIG_DM_PMIC_PFUZE100
164 int power_init_board(void)
165 {
166 	struct udevice *dev;
167 	int ret;
168 	u32 dev_id, rev_id, i;
169 	u32 switch_num = 6;
170 	u32 offset = PFUZE100_SW1CMODE;
171 
172 	ret = pmic_get("pfuze100", &dev);
173 	if (ret == -ENODEV)
174 		return 0;
175 
176 	if (ret != 0)
177 		return ret;
178 
179 	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
180 	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
181 	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
182 
183 	/* set SW1AB staby volatage 0.975V */
184 	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
185 
186 	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
187 	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
188 
189 	/* set SW1C staby volatage 0.975V */
190 	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
191 
192 	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
193 	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
194 
195 	/* Init mode to APS_PFM */
196 	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
197 
198 	for (i = 0; i < switch_num - 1; i++)
199 		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
200 
201 	return 0;
202 }
203 #endif
204 
205 #ifdef CONFIG_FEC_MXC
206 int board_eth_init(bd_t *bis)
207 {
208 	setup_iomux_fec();
209 
210 	return cpu_eth_init(bis);
211 }
212 
213 static int setup_fec(void)
214 {
215 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
216 
217 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
218 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
219 
220 	return enable_fec_anatop_clock(0, ENET_50MHZ);
221 }
222 #endif
223 
224 int board_early_init_f(void)
225 {
226 	setup_iomux_uart();
227 
228 	return 0;
229 }
230 
231 int board_init(void)
232 {
233 	/* address of boot parameters */
234 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
235 
236 #ifdef CONFIG_MXC_SPI
237 	gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
238 	setup_spi();
239 #endif
240 
241 #ifdef	CONFIG_FEC_MXC
242 	setup_fec();
243 #endif
244 
245 	return 0;
246 }
247 
248 int checkboard(void)
249 {
250 	puts("Board: MX6SLEVK\n");
251 
252 	return 0;
253 }
254 
255 #ifdef CONFIG_SPL_BUILD
256 #include <spl.h>
257 #include <libfdt.h>
258 
259 #define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
260 #define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
261 #define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
262 
263 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
264 	{USDHC1_BASE_ADDR},
265 	{USDHC2_BASE_ADDR, 0, 4},
266 	{USDHC3_BASE_ADDR, 0, 4},
267 };
268 
269 int board_mmc_getcd(struct mmc *mmc)
270 {
271 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
272 	int ret = 0;
273 
274 	switch (cfg->esdhc_base) {
275 	case USDHC1_BASE_ADDR:
276 		gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
277 		ret = !gpio_get_value(USDHC1_CD_GPIO);
278 		break;
279 	case USDHC2_BASE_ADDR:
280 		gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
281 		ret = !gpio_get_value(USDHC2_CD_GPIO);
282 		break;
283 	case USDHC3_BASE_ADDR:
284 		gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
285 		ret = !gpio_get_value(USDHC3_CD_GPIO);
286 		break;
287 	}
288 
289 	return ret;
290 }
291 
292 int board_mmc_init(bd_t *bis)
293 {
294 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
295 	u32 val;
296 	u32 port;
297 
298 	val = readl(&src_regs->sbmr1);
299 
300 	/* Boot from USDHC */
301 	port = (val >> 11) & 0x3;
302 	switch (port) {
303 	case 0:
304 		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
305 						 ARRAY_SIZE(usdhc1_pads));
306 		gpio_direction_input(USDHC1_CD_GPIO);
307 		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
308 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
309 		break;
310 	case 1:
311 		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
312 						 ARRAY_SIZE(usdhc2_pads));
313 		gpio_direction_input(USDHC2_CD_GPIO);
314 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
315 		usdhc_cfg[0].max_bus_width = 4;
316 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
317 		break;
318 	case 2:
319 		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
320 						 ARRAY_SIZE(usdhc3_pads));
321 		gpio_direction_input(USDHC3_CD_GPIO);
322 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
323 		usdhc_cfg[0].max_bus_width = 4;
324 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
325 		break;
326 	}
327 
328 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
329 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
330 }
331 
332 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
333 	.dram_sdqs0 = 0x00003030,
334 	.dram_sdqs1 = 0x00003030,
335 	.dram_sdqs2 = 0x00003030,
336 	.dram_sdqs3 = 0x00003030,
337 	.dram_dqm0 = 0x00000030,
338 	.dram_dqm1 = 0x00000030,
339 	.dram_dqm2 = 0x00000030,
340 	.dram_dqm3 = 0x00000030,
341 	.dram_cas  = 0x00000030,
342 	.dram_ras  = 0x00000030,
343 	.dram_sdclk_0 = 0x00000028,
344 	.dram_reset = 0x00000030,
345 	.dram_sdba2 = 0x00000000,
346 	.dram_odt0 = 0x00000008,
347 	.dram_odt1 = 0x00000008,
348 };
349 
350 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
351 	.grp_b0ds = 0x00000030,
352 	.grp_b1ds = 0x00000030,
353 	.grp_b2ds = 0x00000030,
354 	.grp_b3ds = 0x00000030,
355 	.grp_addds = 0x00000030,
356 	.grp_ctlds = 0x00000030,
357 	.grp_ddrmode_ctl = 0x00020000,
358 	.grp_ddrpke = 0x00000000,
359 	.grp_ddrmode = 0x00020000,
360 	.grp_ddr_type = 0x00080000,
361 };
362 
363 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
364 	.p0_mpdgctrl0 =  0x20000000,
365 	.p0_mpdgctrl1 =  0x00000000,
366 	.p0_mprddlctl =  0x4241444a,
367 	.p0_mpwrdlctl =  0x3030312b,
368 	.mpzqlp2ctl = 0x1b4700c7,
369 };
370 
371 static struct mx6_lpddr2_cfg mem_ddr = {
372 	.mem_speed = 800,
373 	.density = 4,
374 	.width = 32,
375 	.banks = 8,
376 	.rowaddr = 14,
377 	.coladdr = 10,
378 	.trcd_lp = 2000,
379 	.trppb_lp = 2000,
380 	.trpab_lp = 2250,
381 	.trasmin = 4200,
382 };
383 
384 static void ccgr_init(void)
385 {
386 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
387 
388 	writel(0xFFFFFFFF, &ccm->CCGR0);
389 	writel(0xFFFFFFFF, &ccm->CCGR1);
390 	writel(0xFFFFFFFF, &ccm->CCGR2);
391 	writel(0xFFFFFFFF, &ccm->CCGR3);
392 	writel(0xFFFFFFFF, &ccm->CCGR4);
393 	writel(0xFFFFFFFF, &ccm->CCGR5);
394 	writel(0xFFFFFFFF, &ccm->CCGR6);
395 
396 	writel(0x00260324, &ccm->cbcmr);
397 }
398 
399 static void spl_dram_init(void)
400 {
401 	struct mx6_ddr_sysinfo sysinfo = {
402 		.dsize = mem_ddr.width / 32,
403 		.cs_density = 20,
404 		.ncs = 2,
405 		.cs1_mirror = 0,
406 		.walat = 0,
407 		.ralat = 2,
408 		.mif3_mode = 3,
409 		.bi_on = 1,
410 		.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
411 		.rtt_nom = 0,
412 		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
413 		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
414 		.ddr_type = DDR_TYPE_LPDDR2,
415 		.refsel = 0,	/* Refresh cycles at 64KHz */
416 		.refr = 3,	/* 4 refresh commands per refresh cycle */
417 	};
418 	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
419 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
420 }
421 
422 void board_init_f(ulong dummy)
423 {
424 	/* setup AIPS and disable watchdog */
425 	arch_cpu_init();
426 
427 	ccgr_init();
428 
429 	/* iomux and setup of i2c */
430 	board_early_init_f();
431 
432 	/* setup GP timer */
433 	timer_init();
434 
435 	/* UART clocks enabled and gd valid - init serial console */
436 	preloader_console_init();
437 
438 	/* DDR initialization */
439 	spl_dram_init();
440 
441 	/* Clear the BSS. */
442 	memset(__bss_start, 0, __bss_end - __bss_start);
443 
444 	/* load/boot image from boot device */
445 	board_init_r(NULL, 0);
446 }
447 #endif
448