1 /*
2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/spi.h>
17 #include <asm/io.h>
18 #include <linux/sizes.h>
19 #include <common.h>
20 #include <fsl_esdhc.h>
21 #include <mmc.h>
22 #include <netdev.h>
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
27 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
28 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
29 
30 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
31 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
32 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
33 
34 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
35 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
36 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
37 
38 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
39 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
40 
41 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
42 
43 int dram_init(void)
44 {
45 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
46 
47 	return 0;
48 }
49 
50 static iomux_v3_cfg_t const uart1_pads[] = {
51 	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
52 	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
53 };
54 
55 static iomux_v3_cfg_t const usdhc2_pads[] = {
56 	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 };
63 
64 static iomux_v3_cfg_t const fec_pads[] = {
65 	MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 	MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 	MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 	MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 	MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 	MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 	MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 	MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 	MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
75 	MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
76 };
77 
78 #ifdef CONFIG_MXC_SPI
79 static iomux_v3_cfg_t ecspi1_pads[] = {
80 	MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
81 	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
82 	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
83 	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
84 };
85 
86 int board_spi_cs_gpio(unsigned bus, unsigned cs)
87 {
88 	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
89 }
90 
91 static void setup_spi(void)
92 {
93 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
94 }
95 #endif
96 
97 static void setup_iomux_uart(void)
98 {
99 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
100 }
101 
102 static void setup_iomux_fec(void)
103 {
104 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
105 
106 	/* Reset LAN8720 PHY */
107 	gpio_direction_output(ETH_PHY_RESET , 0);
108 	udelay(1000);
109 	gpio_set_value(ETH_PHY_RESET, 1);
110 }
111 
112 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
113 	{USDHC2_BASE_ADDR},
114 };
115 
116 int board_mmc_getcd(struct mmc *mmc)
117 {
118 	return 1;	/* Assume boot SD always present */
119 }
120 
121 int board_mmc_init(bd_t *bis)
122 {
123 	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
124 
125 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
126 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
127 }
128 
129 #ifdef CONFIG_FEC_MXC
130 int board_eth_init(bd_t *bis)
131 {
132 	setup_iomux_fec();
133 
134 	return cpu_eth_init(bis);
135 }
136 
137 static int setup_fec(void)
138 {
139 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
140 	int ret;
141 
142 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
143 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
144 
145 	ret = enable_fec_anatop_clock(ENET_50MHz);
146 	if (ret)
147 		return ret;
148 
149 	return 0;
150 }
151 #endif
152 
153 
154 int board_early_init_f(void)
155 {
156 	setup_iomux_uart();
157 #ifdef CONFIG_MXC_SPI
158 	setup_spi();
159 #endif
160 	return 0;
161 }
162 
163 int board_init(void)
164 {
165 	/* address of boot parameters */
166 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
167 
168 #ifdef	CONFIG_FEC_MXC
169 	setup_fec();
170 #endif
171 	return 0;
172 }
173 
174 u32 get_board_rev(void)
175 {
176 	return get_cpu_rev();
177 }
178 
179 int checkboard(void)
180 {
181 	puts("Board: MX6SLEVK\n");
182 
183 	return 0;
184 }
185