1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/boot_mode.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 #include <asm/arch/mxc_hdmi.h> 22 #include <asm/arch/crm_regs.h> 23 #include <linux/fb.h> 24 #include <ipu_pixfmt.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 31 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 32 33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 34 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 35 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 37 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 39 40 int dram_init(void) 41 { 42 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 43 44 return 0; 45 } 46 47 iomux_v3_cfg_t const uart1_pads[] = { 48 MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 49 MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 50 }; 51 52 iomux_v3_cfg_t const enet_pads[] = { 53 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 54 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 55 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 56 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 57 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 58 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 59 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 60 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 61 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 62 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 63 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 64 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 65 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 66 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 67 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 68 /* AR8031 PHY Reset */ 69 MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), 70 }; 71 72 static void setup_iomux_enet(void) 73 { 74 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 75 76 /* Reset AR8031 PHY */ 77 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 78 udelay(500); 79 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 80 } 81 82 iomux_v3_cfg_t const usdhc2_pads[] = { 83 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 94 }; 95 96 iomux_v3_cfg_t const usdhc3_pads[] = { 97 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 108 }; 109 110 iomux_v3_cfg_t const usdhc4_pads[] = { 111 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 115 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117 MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 }; 122 123 static void setup_iomux_uart(void) 124 { 125 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 126 } 127 128 #ifdef CONFIG_FSL_ESDHC 129 struct fsl_esdhc_cfg usdhc_cfg[3] = { 130 {USDHC2_BASE_ADDR}, 131 {USDHC3_BASE_ADDR}, 132 {USDHC4_BASE_ADDR}, 133 }; 134 135 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 136 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 137 138 int board_mmc_getcd(struct mmc *mmc) 139 { 140 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 141 int ret = 0; 142 143 switch (cfg->esdhc_base) { 144 case USDHC2_BASE_ADDR: 145 ret = !gpio_get_value(USDHC2_CD_GPIO); 146 break; 147 case USDHC3_BASE_ADDR: 148 ret = !gpio_get_value(USDHC3_CD_GPIO); 149 break; 150 case USDHC4_BASE_ADDR: 151 ret = 1; /* eMMC/uSDHC4 is always present */ 152 break; 153 } 154 155 return ret; 156 } 157 158 int board_mmc_init(bd_t *bis) 159 { 160 s32 status = 0; 161 int i; 162 163 /* 164 * According to the board_mmc_init() the following map is done: 165 * (U-boot device node) (Physical Port) 166 * mmc0 SD2 167 * mmc1 SD3 168 * mmc2 eMMC 169 */ 170 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 171 switch (i) { 172 case 0: 173 imx_iomux_v3_setup_multiple_pads( 174 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 175 gpio_direction_input(USDHC2_CD_GPIO); 176 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 177 break; 178 case 1: 179 imx_iomux_v3_setup_multiple_pads( 180 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 181 gpio_direction_input(USDHC3_CD_GPIO); 182 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 183 break; 184 case 2: 185 imx_iomux_v3_setup_multiple_pads( 186 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 187 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 188 break; 189 default: 190 printf("Warning: you configured more USDHC controllers" 191 "(%d) then supported by the board (%d)\n", 192 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 193 return status; 194 } 195 196 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 197 } 198 199 return status; 200 } 201 #endif 202 203 int mx6_rgmii_rework(struct phy_device *phydev) 204 { 205 unsigned short val; 206 207 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 208 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 209 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 210 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 211 212 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 213 val &= 0xffe3; 214 val |= 0x18; 215 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 216 217 /* introduce tx clock delay */ 218 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 219 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 220 val |= 0x0100; 221 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 222 223 return 0; 224 } 225 226 int board_phy_config(struct phy_device *phydev) 227 { 228 mx6_rgmii_rework(phydev); 229 230 if (phydev->drv->config) 231 phydev->drv->config(phydev); 232 233 return 0; 234 } 235 236 #if defined(CONFIG_VIDEO_IPUV3) 237 struct display_info_t { 238 int bus; 239 int addr; 240 int pixfmt; 241 int (*detect)(struct display_info_t const *dev); 242 void (*enable)(struct display_info_t const *dev); 243 struct fb_videomode mode; 244 }; 245 246 static int detect_hdmi(struct display_info_t const *dev) 247 { 248 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 249 return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; 250 } 251 252 static void do_enable_hdmi(struct display_info_t const *dev) 253 { 254 imx_enable_hdmi_phy(); 255 } 256 257 static void enable_lvds(struct display_info_t const *dev) 258 { 259 struct iomuxc *iomux = (struct iomuxc *) 260 IOMUXC_BASE_ADDR; 261 u32 reg = readl(&iomux->gpr[2]); 262 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | 263 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT; 264 writel(reg, &iomux->gpr[2]); 265 } 266 static struct display_info_t const displays[] = {{ 267 .bus = -1, 268 .addr = 0, 269 .pixfmt = IPU_PIX_FMT_RGB24, 270 .detect = detect_hdmi, 271 .enable = do_enable_hdmi, 272 .mode = { 273 .name = "HDMI", 274 .refresh = 60, 275 .xres = 1024, 276 .yres = 768, 277 .pixclock = 15385, 278 .left_margin = 220, 279 .right_margin = 40, 280 .upper_margin = 21, 281 .lower_margin = 7, 282 .hsync_len = 60, 283 .vsync_len = 10, 284 .sync = FB_SYNC_EXT, 285 .vmode = FB_VMODE_NONINTERLACED 286 } }, { 287 .bus = -1, 288 .addr = 0, 289 .pixfmt = IPU_PIX_FMT_LVDS666, 290 .detect = NULL, 291 .enable = enable_lvds, 292 .mode = { 293 .name = "Hannstar-XGA", 294 .refresh = 60, 295 .xres = 1024, 296 .yres = 768, 297 .pixclock = 15385, 298 .left_margin = 220, 299 .right_margin = 40, 300 .upper_margin = 21, 301 .lower_margin = 7, 302 .hsync_len = 60, 303 .vsync_len = 10, 304 .sync = FB_SYNC_EXT, 305 .vmode = FB_VMODE_NONINTERLACED 306 } } }; 307 308 int board_video_skip(void) 309 { 310 int i; 311 int ret; 312 char const *panel = getenv("panel"); 313 if (!panel) { 314 for (i = 0; i < ARRAY_SIZE(displays); i++) { 315 struct display_info_t const *dev = displays+i; 316 if (dev->detect && dev->detect(dev)) { 317 panel = dev->mode.name; 318 printf("auto-detected panel %s\n", panel); 319 break; 320 } 321 } 322 if (!panel) { 323 panel = displays[0].mode.name; 324 printf("No panel detected: default to %s\n", panel); 325 i = 0; 326 } 327 } else { 328 for (i = 0; i < ARRAY_SIZE(displays); i++) { 329 if (!strcmp(panel, displays[i].mode.name)) 330 break; 331 } 332 } 333 if (i < ARRAY_SIZE(displays)) { 334 ret = ipuv3_fb_init(&displays[i].mode, 0, 335 displays[i].pixfmt); 336 if (!ret) { 337 displays[i].enable(displays+i); 338 printf("Display: %s (%ux%u)\n", 339 displays[i].mode.name, 340 displays[i].mode.xres, 341 displays[i].mode.yres); 342 } else 343 printf("LCD %s cannot be configured: %d\n", 344 displays[i].mode.name, ret); 345 } else { 346 printf("unsupported panel %s\n", panel); 347 return -EINVAL; 348 } 349 350 return 0; 351 } 352 353 static void setup_display(void) 354 { 355 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 356 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 357 int reg; 358 359 enable_ipu_clock(); 360 imx_setup_hdmi(); 361 362 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ 363 reg = __raw_readl(&mxc_ccm->CCGR3); 364 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 365 writel(reg, &mxc_ccm->CCGR3); 366 367 /* set LDB0, LDB1 clk select to 011/011 */ 368 reg = readl(&mxc_ccm->cs2cdr); 369 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 370 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 371 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 372 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 373 writel(reg, &mxc_ccm->cs2cdr); 374 375 reg = readl(&mxc_ccm->cscmr2); 376 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 377 writel(reg, &mxc_ccm->cscmr2); 378 379 reg = readl(&mxc_ccm->chsccdr); 380 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 381 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 382 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 383 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 384 writel(reg, &mxc_ccm->chsccdr); 385 386 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 387 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW 388 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 389 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 390 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 391 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 392 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 393 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED 394 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; 395 writel(reg, &iomux->gpr[2]); 396 397 reg = readl(&iomux->gpr[3]); 398 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK 399 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 400 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 401 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); 402 writel(reg, &iomux->gpr[3]); 403 } 404 #endif /* CONFIG_VIDEO_IPUV3 */ 405 406 /* 407 * Do not overwrite the console 408 * Use always serial for U-Boot console 409 */ 410 int overwrite_console(void) 411 { 412 return 1; 413 } 414 415 int board_eth_init(bd_t *bis) 416 { 417 int ret; 418 419 setup_iomux_enet(); 420 421 ret = cpu_eth_init(bis); 422 if (ret) 423 printf("FEC MXC: %s:failed\n", __func__); 424 425 return ret; 426 } 427 428 int board_early_init_f(void) 429 { 430 setup_iomux_uart(); 431 #if defined(CONFIG_VIDEO_IPUV3) 432 setup_display(); 433 #endif 434 435 return 0; 436 } 437 438 int board_init(void) 439 { 440 /* address of boot parameters */ 441 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 442 443 return 0; 444 } 445 446 #ifdef CONFIG_CMD_BMODE 447 static const struct boot_mode board_boot_modes[] = { 448 /* 4 bit bus width */ 449 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 450 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 451 /* 8 bit bus width */ 452 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 453 {NULL, 0}, 454 }; 455 #endif 456 457 int board_late_init(void) 458 { 459 #ifdef CONFIG_CMD_BMODE 460 add_board_boot_modes(board_boot_modes); 461 #endif 462 463 return 0; 464 } 465 466 int checkboard(void) 467 { 468 puts("Board: MX6-SabreSD\n"); 469 return 0; 470 } 471