1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Freescale Semiconductor, Inc. 4 * 5 * Author: Fabio Estevam <fabio.estevam@freescale.com> 6 */ 7 8 #include <asm/arch/clock.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/iomux.h> 11 #include <asm/arch/mx6-pins.h> 12 #include <asm/mach-imx/spi.h> 13 #include <linux/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-imx/mxc_i2c.h> 16 #include <asm/mach-imx/iomux-v3.h> 17 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/video.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <miiphy.h> 22 #include <netdev.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/arch/crm_regs.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <i2c.h> 28 #include <input.h> 29 #include <power/pmic.h> 30 #include <power/pfuze100_pmic.h> 31 #include "../common/pfuze.h" 32 #include <usb.h> 33 #include <usb/ehci-ci.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 39 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 40 41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 43 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 44 45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 47 48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 49 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 50 51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 53 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 54 55 #define I2C_PMIC 1 56 57 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 58 59 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) 60 61 #define KEY_VOL_UP IMX_GPIO_NR(1, 4) 62 63 int dram_init(void) 64 { 65 gd->ram_size = imx_ddr_size(); 66 return 0; 67 } 68 69 static iomux_v3_cfg_t const uart1_pads[] = { 70 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 71 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 72 }; 73 74 static iomux_v3_cfg_t const enet_pads[] = { 75 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 76 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 77 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 78 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 79 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 80 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 81 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 82 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 83 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), 84 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 85 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 86 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 87 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 88 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 89 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 90 /* AR8031 PHY Reset */ 91 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), 92 }; 93 94 static void setup_iomux_enet(void) 95 { 96 SETUP_IOMUX_PADS(enet_pads); 97 98 /* Reset AR8031 PHY */ 99 gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset"); 100 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 101 mdelay(10); 102 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 103 udelay(100); 104 } 105 106 static iomux_v3_cfg_t const usdhc2_pads[] = { 107 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 108 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 109 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 110 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 111 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 112 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 113 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 114 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 115 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 116 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 117 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ 118 }; 119 120 static iomux_v3_cfg_t const usdhc3_pads[] = { 121 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 122 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 123 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 124 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 125 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 126 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 127 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 128 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 129 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 130 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 131 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ 132 }; 133 134 static iomux_v3_cfg_t const usdhc4_pads[] = { 135 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 136 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 137 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 138 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 139 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 140 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 141 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 142 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 143 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 144 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 145 }; 146 147 static iomux_v3_cfg_t const ecspi1_pads[] = { 148 IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), 149 IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), 150 IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), 151 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), 152 }; 153 154 static iomux_v3_cfg_t const rgb_pads[] = { 155 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), 156 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)), 157 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 158 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 159 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 160 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 161 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 162 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 163 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 164 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 165 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 166 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 167 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 168 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)), 169 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)), 170 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)), 171 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)), 172 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)), 173 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)), 174 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)), 175 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)), 176 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 177 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)), 178 IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)), 179 IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)), 180 IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)), 181 IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)), 182 IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)), 183 IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)), 184 }; 185 186 static iomux_v3_cfg_t const bl_pads[] = { 187 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)), 188 }; 189 190 static void enable_backlight(void) 191 { 192 SETUP_IOMUX_PADS(bl_pads); 193 gpio_request(DISP0_PWR_EN, "Display Power Enable"); 194 gpio_direction_output(DISP0_PWR_EN, 1); 195 } 196 197 static void enable_rgb(struct display_info_t const *dev) 198 { 199 SETUP_IOMUX_PADS(rgb_pads); 200 enable_backlight(); 201 } 202 203 static void enable_lvds(struct display_info_t const *dev) 204 { 205 enable_backlight(); 206 } 207 208 static struct i2c_pads_info mx6q_i2c_pad_info1 = { 209 .scl = { 210 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 211 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 212 .gp = IMX_GPIO_NR(4, 12) 213 }, 214 .sda = { 215 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 216 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 217 .gp = IMX_GPIO_NR(4, 13) 218 } 219 }; 220 221 static struct i2c_pads_info mx6dl_i2c_pad_info1 = { 222 .scl = { 223 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 224 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 225 .gp = IMX_GPIO_NR(4, 12) 226 }, 227 .sda = { 228 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 229 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 230 .gp = IMX_GPIO_NR(4, 13) 231 } 232 }; 233 234 static void setup_spi(void) 235 { 236 SETUP_IOMUX_PADS(ecspi1_pads); 237 } 238 239 iomux_v3_cfg_t const pcie_pads[] = { 240 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */ 241 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */ 242 }; 243 244 static void setup_pcie(void) 245 { 246 SETUP_IOMUX_PADS(pcie_pads); 247 } 248 249 iomux_v3_cfg_t const di0_pads[] = { 250 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */ 251 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */ 252 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */ 253 }; 254 255 static void setup_iomux_uart(void) 256 { 257 SETUP_IOMUX_PADS(uart1_pads); 258 } 259 260 #ifdef CONFIG_FSL_ESDHC 261 struct fsl_esdhc_cfg usdhc_cfg[3] = { 262 {USDHC2_BASE_ADDR}, 263 {USDHC3_BASE_ADDR}, 264 {USDHC4_BASE_ADDR}, 265 }; 266 267 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 268 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 269 270 int board_mmc_get_env_dev(int devno) 271 { 272 return devno - 1; 273 } 274 275 int board_mmc_getcd(struct mmc *mmc) 276 { 277 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 278 int ret = 0; 279 280 switch (cfg->esdhc_base) { 281 case USDHC2_BASE_ADDR: 282 ret = !gpio_get_value(USDHC2_CD_GPIO); 283 break; 284 case USDHC3_BASE_ADDR: 285 ret = !gpio_get_value(USDHC3_CD_GPIO); 286 break; 287 case USDHC4_BASE_ADDR: 288 ret = 1; /* eMMC/uSDHC4 is always present */ 289 break; 290 } 291 292 return ret; 293 } 294 295 int board_mmc_init(bd_t *bis) 296 { 297 #ifndef CONFIG_SPL_BUILD 298 int ret; 299 int i; 300 301 /* 302 * According to the board_mmc_init() the following map is done: 303 * (U-Boot device node) (Physical Port) 304 * mmc0 SD2 305 * mmc1 SD3 306 * mmc2 eMMC 307 */ 308 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 309 switch (i) { 310 case 0: 311 SETUP_IOMUX_PADS(usdhc2_pads); 312 gpio_request(USDHC2_CD_GPIO, "USDHC2 CD"); 313 gpio_direction_input(USDHC2_CD_GPIO); 314 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 315 break; 316 case 1: 317 SETUP_IOMUX_PADS(usdhc3_pads); 318 gpio_request(USDHC3_CD_GPIO, "USDHC3 CD"); 319 gpio_direction_input(USDHC3_CD_GPIO); 320 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 321 break; 322 case 2: 323 SETUP_IOMUX_PADS(usdhc4_pads); 324 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 325 break; 326 default: 327 printf("Warning: you configured more USDHC controllers" 328 "(%d) then supported by the board (%d)\n", 329 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 330 return -EINVAL; 331 } 332 333 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 334 if (ret) 335 return ret; 336 } 337 338 return 0; 339 #else 340 struct src *psrc = (struct src *)SRC_BASE_ADDR; 341 unsigned reg = readl(&psrc->sbmr1) >> 11; 342 /* 343 * Upon reading BOOT_CFG register the following map is done: 344 * Bit 11 and 12 of BOOT_CFG register can determine the current 345 * mmc port 346 * 0x1 SD1 347 * 0x2 SD2 348 * 0x3 SD4 349 */ 350 351 switch (reg & 0x3) { 352 case 0x1: 353 SETUP_IOMUX_PADS(usdhc2_pads); 354 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 355 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 356 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 357 break; 358 case 0x2: 359 SETUP_IOMUX_PADS(usdhc3_pads); 360 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 361 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 362 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 363 break; 364 case 0x3: 365 SETUP_IOMUX_PADS(usdhc4_pads); 366 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 367 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 368 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 369 break; 370 } 371 372 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 373 #endif 374 } 375 #endif 376 377 static int ar8031_phy_fixup(struct phy_device *phydev) 378 { 379 unsigned short val; 380 381 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 382 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 383 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 384 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 385 386 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 387 val &= 0xffe3; 388 val |= 0x18; 389 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 390 391 /* introduce tx clock delay */ 392 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 393 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 394 val |= 0x0100; 395 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 396 397 return 0; 398 } 399 400 int board_phy_config(struct phy_device *phydev) 401 { 402 ar8031_phy_fixup(phydev); 403 404 if (phydev->drv->config) 405 phydev->drv->config(phydev); 406 407 return 0; 408 } 409 410 #if defined(CONFIG_VIDEO_IPUV3) 411 static void disable_lvds(struct display_info_t const *dev) 412 { 413 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 414 415 int reg = readl(&iomux->gpr[2]); 416 417 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | 418 IOMUXC_GPR2_LVDS_CH1_MODE_MASK); 419 420 writel(reg, &iomux->gpr[2]); 421 } 422 423 static void do_enable_hdmi(struct display_info_t const *dev) 424 { 425 disable_lvds(dev); 426 imx_enable_hdmi_phy(); 427 } 428 429 struct display_info_t const displays[] = {{ 430 .bus = -1, 431 .addr = 0, 432 .pixfmt = IPU_PIX_FMT_RGB666, 433 .detect = NULL, 434 .enable = enable_lvds, 435 .mode = { 436 .name = "Hannstar-XGA", 437 .refresh = 60, 438 .xres = 1024, 439 .yres = 768, 440 .pixclock = 15384, 441 .left_margin = 160, 442 .right_margin = 24, 443 .upper_margin = 29, 444 .lower_margin = 3, 445 .hsync_len = 136, 446 .vsync_len = 6, 447 .sync = FB_SYNC_EXT, 448 .vmode = FB_VMODE_NONINTERLACED 449 } }, { 450 .bus = -1, 451 .addr = 0, 452 .pixfmt = IPU_PIX_FMT_RGB24, 453 .detect = detect_hdmi, 454 .enable = do_enable_hdmi, 455 .mode = { 456 .name = "HDMI", 457 .refresh = 60, 458 .xres = 1024, 459 .yres = 768, 460 .pixclock = 15384, 461 .left_margin = 160, 462 .right_margin = 24, 463 .upper_margin = 29, 464 .lower_margin = 3, 465 .hsync_len = 136, 466 .vsync_len = 6, 467 .sync = FB_SYNC_EXT, 468 .vmode = FB_VMODE_NONINTERLACED 469 } }, { 470 .bus = 0, 471 .addr = 0, 472 .pixfmt = IPU_PIX_FMT_RGB24, 473 .detect = NULL, 474 .enable = enable_rgb, 475 .mode = { 476 .name = "SEIKO-WVGA", 477 .refresh = 60, 478 .xres = 800, 479 .yres = 480, 480 .pixclock = 29850, 481 .left_margin = 89, 482 .right_margin = 164, 483 .upper_margin = 23, 484 .lower_margin = 10, 485 .hsync_len = 10, 486 .vsync_len = 10, 487 .sync = 0, 488 .vmode = FB_VMODE_NONINTERLACED 489 } } }; 490 size_t display_count = ARRAY_SIZE(displays); 491 492 static void setup_display(void) 493 { 494 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 495 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 496 int reg; 497 498 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ 499 SETUP_IOMUX_PADS(di0_pads); 500 501 enable_ipu_clock(); 502 imx_setup_hdmi(); 503 504 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ 505 reg = readl(&mxc_ccm->CCGR3); 506 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 507 writel(reg, &mxc_ccm->CCGR3); 508 509 /* set LDB0, LDB1 clk select to 011/011 */ 510 reg = readl(&mxc_ccm->cs2cdr); 511 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 512 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 513 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 514 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 515 writel(reg, &mxc_ccm->cs2cdr); 516 517 reg = readl(&mxc_ccm->cscmr2); 518 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 519 writel(reg, &mxc_ccm->cscmr2); 520 521 reg = readl(&mxc_ccm->chsccdr); 522 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 523 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 524 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 525 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 526 writel(reg, &mxc_ccm->chsccdr); 527 528 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 529 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW 530 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 531 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 532 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 533 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 534 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 535 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED 536 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; 537 writel(reg, &iomux->gpr[2]); 538 539 reg = readl(&iomux->gpr[3]); 540 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK 541 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 542 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 543 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); 544 writel(reg, &iomux->gpr[3]); 545 } 546 #endif /* CONFIG_VIDEO_IPUV3 */ 547 548 /* 549 * Do not overwrite the console 550 * Use always serial for U-Boot console 551 */ 552 int overwrite_console(void) 553 { 554 return 1; 555 } 556 557 int board_eth_init(bd_t *bis) 558 { 559 setup_iomux_enet(); 560 setup_pcie(); 561 562 return cpu_eth_init(bis); 563 } 564 565 #ifdef CONFIG_USB_EHCI_MX6 566 #define USB_OTHERREGS_OFFSET 0x800 567 #define UCTRL_PWR_POL (1 << 9) 568 569 static iomux_v3_cfg_t const usb_otg_pads[] = { 570 IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)), 571 IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), 572 }; 573 574 static iomux_v3_cfg_t const usb_hc1_pads[] = { 575 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 576 }; 577 578 static void setup_usb(void) 579 { 580 SETUP_IOMUX_PADS(usb_otg_pads); 581 582 /* 583 * set daisy chain for otg_pin_id on 6q. 584 * for 6dl, this bit is reserved 585 */ 586 imx_iomux_set_gpr_register(1, 13, 1, 0); 587 588 SETUP_IOMUX_PADS(usb_hc1_pads); 589 } 590 591 int board_ehci_hcd_init(int port) 592 { 593 u32 *usbnc_usb_ctrl; 594 595 if (port > 1) 596 return -EINVAL; 597 598 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 599 port * 4); 600 601 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 602 603 return 0; 604 } 605 606 int board_ehci_power(int port, int on) 607 { 608 switch (port) { 609 case 0: 610 break; 611 case 1: 612 if (on) 613 gpio_direction_output(IMX_GPIO_NR(1, 29), 1); 614 else 615 gpio_direction_output(IMX_GPIO_NR(1, 29), 0); 616 break; 617 default: 618 printf("MXC USB port %d not yet supported\n", port); 619 return -EINVAL; 620 } 621 622 return 0; 623 } 624 #endif 625 626 int board_early_init_f(void) 627 { 628 setup_iomux_uart(); 629 630 return 0; 631 } 632 633 int board_init(void) 634 { 635 /* address of boot parameters */ 636 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 637 638 #ifdef CONFIG_MXC_SPI 639 setup_spi(); 640 #endif 641 if (is_mx6dq() || is_mx6dqp()) 642 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); 643 else 644 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); 645 #if defined(CONFIG_VIDEO_IPUV3) 646 setup_display(); 647 #endif 648 #ifdef CONFIG_USB_EHCI_MX6 649 setup_usb(); 650 #endif 651 652 return 0; 653 } 654 655 int power_init_board(void) 656 { 657 struct pmic *p; 658 unsigned int reg; 659 int ret; 660 661 p = pfuze_common_init(I2C_PMIC); 662 if (!p) 663 return -ENODEV; 664 665 ret = pfuze_mode_init(p, APS_PFM); 666 if (ret < 0) 667 return ret; 668 669 /* Increase VGEN3 from 2.5 to 2.8V */ 670 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); 671 reg &= ~LDO_VOL_MASK; 672 reg |= LDOB_2_80V; 673 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); 674 675 /* Increase VGEN5 from 2.8 to 3V */ 676 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 677 reg &= ~LDO_VOL_MASK; 678 reg |= LDOB_3_00V; 679 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 680 681 return 0; 682 } 683 684 #ifdef CONFIG_MXC_SPI 685 int board_spi_cs_gpio(unsigned bus, unsigned cs) 686 { 687 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; 688 } 689 #endif 690 691 #ifdef CONFIG_CMD_BMODE 692 static const struct boot_mode board_boot_modes[] = { 693 /* 4 bit bus width */ 694 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 695 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 696 /* 8 bit bus width */ 697 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, 698 {NULL, 0}, 699 }; 700 #endif 701 702 int board_late_init(void) 703 { 704 #ifdef CONFIG_CMD_BMODE 705 add_board_boot_modes(board_boot_modes); 706 #endif 707 708 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 709 env_set("board_name", "SABRESD"); 710 711 if (is_mx6dqp()) 712 env_set("board_rev", "MX6QP"); 713 else if (is_mx6dq()) 714 env_set("board_rev", "MX6Q"); 715 else if (is_mx6sdl()) 716 env_set("board_rev", "MX6DL"); 717 #endif 718 719 return 0; 720 } 721 722 int checkboard(void) 723 { 724 puts("Board: MX6-SabreSD\n"); 725 return 0; 726 } 727 728 #ifdef CONFIG_SPL_BUILD 729 #include <asm/arch/mx6-ddr.h> 730 #include <spl.h> 731 #include <linux/libfdt.h> 732 733 #ifdef CONFIG_SPL_OS_BOOT 734 int spl_start_uboot(void) 735 { 736 gpio_request(KEY_VOL_UP, "KEY Volume UP"); 737 gpio_direction_input(KEY_VOL_UP); 738 739 /* Only enter in Falcon mode if KEY_VOL_UP is pressed */ 740 return gpio_get_value(KEY_VOL_UP); 741 } 742 #endif 743 744 static void ccgr_init(void) 745 { 746 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 747 748 writel(0x00C03F3F, &ccm->CCGR0); 749 writel(0x0030FC03, &ccm->CCGR1); 750 writel(0x0FFFC000, &ccm->CCGR2); 751 writel(0x3FF00000, &ccm->CCGR3); 752 writel(0x00FFF300, &ccm->CCGR4); 753 writel(0x0F0000C3, &ccm->CCGR5); 754 writel(0x000003FF, &ccm->CCGR6); 755 } 756 757 static int mx6q_dcd_table[] = { 758 0x020e0798, 0x000C0000, 759 0x020e0758, 0x00000000, 760 0x020e0588, 0x00000030, 761 0x020e0594, 0x00000030, 762 0x020e056c, 0x00000030, 763 0x020e0578, 0x00000030, 764 0x020e074c, 0x00000030, 765 0x020e057c, 0x00000030, 766 0x020e058c, 0x00000000, 767 0x020e059c, 0x00000030, 768 0x020e05a0, 0x00000030, 769 0x020e078c, 0x00000030, 770 0x020e0750, 0x00020000, 771 0x020e05a8, 0x00000030, 772 0x020e05b0, 0x00000030, 773 0x020e0524, 0x00000030, 774 0x020e051c, 0x00000030, 775 0x020e0518, 0x00000030, 776 0x020e050c, 0x00000030, 777 0x020e05b8, 0x00000030, 778 0x020e05c0, 0x00000030, 779 0x020e0774, 0x00020000, 780 0x020e0784, 0x00000030, 781 0x020e0788, 0x00000030, 782 0x020e0794, 0x00000030, 783 0x020e079c, 0x00000030, 784 0x020e07a0, 0x00000030, 785 0x020e07a4, 0x00000030, 786 0x020e07a8, 0x00000030, 787 0x020e0748, 0x00000030, 788 0x020e05ac, 0x00000030, 789 0x020e05b4, 0x00000030, 790 0x020e0528, 0x00000030, 791 0x020e0520, 0x00000030, 792 0x020e0514, 0x00000030, 793 0x020e0510, 0x00000030, 794 0x020e05bc, 0x00000030, 795 0x020e05c4, 0x00000030, 796 0x021b0800, 0xa1390003, 797 0x021b080c, 0x001F001F, 798 0x021b0810, 0x001F001F, 799 0x021b480c, 0x001F001F, 800 0x021b4810, 0x001F001F, 801 0x021b083c, 0x43270338, 802 0x021b0840, 0x03200314, 803 0x021b483c, 0x431A032F, 804 0x021b4840, 0x03200263, 805 0x021b0848, 0x4B434748, 806 0x021b4848, 0x4445404C, 807 0x021b0850, 0x38444542, 808 0x021b4850, 0x4935493A, 809 0x021b081c, 0x33333333, 810 0x021b0820, 0x33333333, 811 0x021b0824, 0x33333333, 812 0x021b0828, 0x33333333, 813 0x021b481c, 0x33333333, 814 0x021b4820, 0x33333333, 815 0x021b4824, 0x33333333, 816 0x021b4828, 0x33333333, 817 0x021b08b8, 0x00000800, 818 0x021b48b8, 0x00000800, 819 0x021b0004, 0x00020036, 820 0x021b0008, 0x09444040, 821 0x021b000c, 0x555A7975, 822 0x021b0010, 0xFF538F64, 823 0x021b0014, 0x01FF00DB, 824 0x021b0018, 0x00001740, 825 0x021b001c, 0x00008000, 826 0x021b002c, 0x000026d2, 827 0x021b0030, 0x005A1023, 828 0x021b0040, 0x00000027, 829 0x021b0000, 0x831A0000, 830 0x021b001c, 0x04088032, 831 0x021b001c, 0x00008033, 832 0x021b001c, 0x00048031, 833 0x021b001c, 0x09408030, 834 0x021b001c, 0x04008040, 835 0x021b0020, 0x00005800, 836 0x021b0818, 0x00011117, 837 0x021b4818, 0x00011117, 838 0x021b0004, 0x00025576, 839 0x021b0404, 0x00011006, 840 0x021b001c, 0x00000000, 841 }; 842 843 static int mx6qp_dcd_table[] = { 844 0x020e0798, 0x000c0000, 845 0x020e0758, 0x00000000, 846 0x020e0588, 0x00000030, 847 0x020e0594, 0x00000030, 848 0x020e056c, 0x00000030, 849 0x020e0578, 0x00000030, 850 0x020e074c, 0x00000030, 851 0x020e057c, 0x00000030, 852 0x020e058c, 0x00000000, 853 0x020e059c, 0x00000030, 854 0x020e05a0, 0x00000030, 855 0x020e078c, 0x00000030, 856 0x020e0750, 0x00020000, 857 0x020e05a8, 0x00000030, 858 0x020e05b0, 0x00000030, 859 0x020e0524, 0x00000030, 860 0x020e051c, 0x00000030, 861 0x020e0518, 0x00000030, 862 0x020e050c, 0x00000030, 863 0x020e05b8, 0x00000030, 864 0x020e05c0, 0x00000030, 865 0x020e0774, 0x00020000, 866 0x020e0784, 0x00000030, 867 0x020e0788, 0x00000030, 868 0x020e0794, 0x00000030, 869 0x020e079c, 0x00000030, 870 0x020e07a0, 0x00000030, 871 0x020e07a4, 0x00000030, 872 0x020e07a8, 0x00000030, 873 0x020e0748, 0x00000030, 874 0x020e05ac, 0x00000030, 875 0x020e05b4, 0x00000030, 876 0x020e0528, 0x00000030, 877 0x020e0520, 0x00000030, 878 0x020e0514, 0x00000030, 879 0x020e0510, 0x00000030, 880 0x020e05bc, 0x00000030, 881 0x020e05c4, 0x00000030, 882 0x021b0800, 0xa1390003, 883 0x021b080c, 0x001b001e, 884 0x021b0810, 0x002e0029, 885 0x021b480c, 0x001b002a, 886 0x021b4810, 0x0019002c, 887 0x021b083c, 0x43240334, 888 0x021b0840, 0x0324031a, 889 0x021b483c, 0x43340344, 890 0x021b4840, 0x03280276, 891 0x021b0848, 0x44383A3E, 892 0x021b4848, 0x3C3C3846, 893 0x021b0850, 0x2e303230, 894 0x021b4850, 0x38283E34, 895 0x021b081c, 0x33333333, 896 0x021b0820, 0x33333333, 897 0x021b0824, 0x33333333, 898 0x021b0828, 0x33333333, 899 0x021b481c, 0x33333333, 900 0x021b4820, 0x33333333, 901 0x021b4824, 0x33333333, 902 0x021b4828, 0x33333333, 903 0x021b08c0, 0x24912249, 904 0x021b48c0, 0x24914289, 905 0x021b08b8, 0x00000800, 906 0x021b48b8, 0x00000800, 907 0x021b0004, 0x00020036, 908 0x021b0008, 0x24444040, 909 0x021b000c, 0x555A7955, 910 0x021b0010, 0xFF320F64, 911 0x021b0014, 0x01ff00db, 912 0x021b0018, 0x00001740, 913 0x021b001c, 0x00008000, 914 0x021b002c, 0x000026d2, 915 0x021b0030, 0x005A1023, 916 0x021b0040, 0x00000027, 917 0x021b0400, 0x14420000, 918 0x021b0000, 0x831A0000, 919 0x021b0890, 0x00400C58, 920 0x00bb0008, 0x00000000, 921 0x00bb000c, 0x2891E41A, 922 0x00bb0038, 0x00000564, 923 0x00bb0014, 0x00000040, 924 0x00bb0028, 0x00000020, 925 0x00bb002c, 0x00000020, 926 0x021b001c, 0x04088032, 927 0x021b001c, 0x00008033, 928 0x021b001c, 0x00048031, 929 0x021b001c, 0x09408030, 930 0x021b001c, 0x04008040, 931 0x021b0020, 0x00005800, 932 0x021b0818, 0x00011117, 933 0x021b4818, 0x00011117, 934 0x021b0004, 0x00025576, 935 0x021b0404, 0x00011006, 936 0x021b001c, 0x00000000, 937 }; 938 939 static int mx6dl_dcd_table[] = { 940 0x020e0774, 0x000C0000, 941 0x020e0754, 0x00000000, 942 0x020e04ac, 0x00000030, 943 0x020e04b0, 0x00000030, 944 0x020e0464, 0x00000030, 945 0x020e0490, 0x00000030, 946 0x020e074c, 0x00000030, 947 0x020e0494, 0x00000030, 948 0x020e04a0, 0x00000000, 949 0x020e04b4, 0x00000030, 950 0x020e04b8, 0x00000030, 951 0x020e076c, 0x00000030, 952 0x020e0750, 0x00020000, 953 0x020e04bc, 0x00000030, 954 0x020e04c0, 0x00000030, 955 0x020e04c4, 0x00000030, 956 0x020e04c8, 0x00000030, 957 0x020e04cc, 0x00000030, 958 0x020e04d0, 0x00000030, 959 0x020e04d4, 0x00000030, 960 0x020e04d8, 0x00000030, 961 0x020e0760, 0x00020000, 962 0x020e0764, 0x00000030, 963 0x020e0770, 0x00000030, 964 0x020e0778, 0x00000030, 965 0x020e077c, 0x00000030, 966 0x020e0780, 0x00000030, 967 0x020e0784, 0x00000030, 968 0x020e078c, 0x00000030, 969 0x020e0748, 0x00000030, 970 0x020e0470, 0x00000030, 971 0x020e0474, 0x00000030, 972 0x020e0478, 0x00000030, 973 0x020e047c, 0x00000030, 974 0x020e0480, 0x00000030, 975 0x020e0484, 0x00000030, 976 0x020e0488, 0x00000030, 977 0x020e048c, 0x00000030, 978 0x021b0800, 0xa1390003, 979 0x021b080c, 0x001F001F, 980 0x021b0810, 0x001F001F, 981 0x021b480c, 0x001F001F, 982 0x021b4810, 0x001F001F, 983 0x021b083c, 0x4220021F, 984 0x021b0840, 0x0207017E, 985 0x021b483c, 0x4201020C, 986 0x021b4840, 0x01660172, 987 0x021b0848, 0x4A4D4E4D, 988 0x021b4848, 0x4A4F5049, 989 0x021b0850, 0x3F3C3D31, 990 0x021b4850, 0x3238372B, 991 0x021b081c, 0x33333333, 992 0x021b0820, 0x33333333, 993 0x021b0824, 0x33333333, 994 0x021b0828, 0x33333333, 995 0x021b481c, 0x33333333, 996 0x021b4820, 0x33333333, 997 0x021b4824, 0x33333333, 998 0x021b4828, 0x33333333, 999 0x021b08b8, 0x00000800, 1000 0x021b48b8, 0x00000800, 1001 0x021b0004, 0x0002002D, 1002 0x021b0008, 0x00333030, 1003 0x021b000c, 0x3F435313, 1004 0x021b0010, 0xB66E8B63, 1005 0x021b0014, 0x01FF00DB, 1006 0x021b0018, 0x00001740, 1007 0x021b001c, 0x00008000, 1008 0x021b002c, 0x000026d2, 1009 0x021b0030, 0x00431023, 1010 0x021b0040, 0x00000027, 1011 0x021b0000, 0x831A0000, 1012 0x021b001c, 0x04008032, 1013 0x021b001c, 0x00008033, 1014 0x021b001c, 0x00048031, 1015 0x021b001c, 0x05208030, 1016 0x021b001c, 0x04008040, 1017 0x021b0020, 0x00005800, 1018 0x021b0818, 0x00011117, 1019 0x021b4818, 0x00011117, 1020 0x021b0004, 0x0002556D, 1021 0x021b0404, 0x00011006, 1022 0x021b001c, 0x00000000, 1023 }; 1024 1025 static void ddr_init(int *table, int size) 1026 { 1027 int i; 1028 1029 for (i = 0; i < size / 2 ; i++) 1030 writel(table[2 * i + 1], table[2 * i]); 1031 } 1032 1033 static void spl_dram_init(void) 1034 { 1035 if (is_mx6dq()) 1036 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); 1037 else if (is_mx6dqp()) 1038 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); 1039 else if (is_mx6sdl()) 1040 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); 1041 } 1042 1043 void board_init_f(ulong dummy) 1044 { 1045 /* DDR initialization */ 1046 spl_dram_init(); 1047 1048 /* setup AIPS and disable watchdog */ 1049 arch_cpu_init(); 1050 1051 ccgr_init(); 1052 gpr_init(); 1053 1054 /* iomux and setup of i2c */ 1055 board_early_init_f(); 1056 1057 /* setup GP timer */ 1058 timer_init(); 1059 1060 /* UART clocks enabled and gd valid - init serial console */ 1061 preloader_console_init(); 1062 1063 /* Clear the BSS. */ 1064 memset(__bss_start, 0, __bss_end - __bss_start); 1065 1066 /* load/boot image from boot device */ 1067 board_init_r(NULL, 0); 1068 } 1069 #endif 1070 1071 #ifdef CONFIG_SPL_LOAD_FIT 1072 int board_fit_config_name_match(const char *name) 1073 { 1074 if (is_mx6dq()) { 1075 if (!strcmp(name, "imx6q-sabresd")) 1076 return 0; 1077 } else if (is_mx6dqp()) { 1078 if (!strcmp(name, "imx6qp-sabresd")) 1079 return 0; 1080 } else if (is_mx6dl()) { 1081 if (!strcmp(name, "imx6dl-sabresd")) 1082 return 0; 1083 } 1084 1085 return -1; 1086 } 1087 #endif 1088