1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/mxc_i2c.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/video.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <miiphy.h> 22 #include <netdev.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/arch/crm_regs.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <i2c.h> 28 #include <power/pmic.h> 29 #include <power/pfuze100_pmic.h> 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 34 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 35 36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 38 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 42 43 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 44 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 45 46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 48 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 49 50 #define I2C_PMIC 1 51 52 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 53 54 int dram_init(void) 55 { 56 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 57 58 return 0; 59 } 60 61 iomux_v3_cfg_t const uart1_pads[] = { 62 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 63 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 64 }; 65 66 iomux_v3_cfg_t const enet_pads[] = { 67 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 68 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 69 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 70 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 71 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 72 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 /* AR8031 PHY Reset */ 83 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 84 }; 85 86 static void setup_iomux_enet(void) 87 { 88 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 89 90 /* Reset AR8031 PHY */ 91 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 92 udelay(500); 93 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 94 } 95 96 iomux_v3_cfg_t const usdhc2_pads[] = { 97 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 108 }; 109 110 iomux_v3_cfg_t const usdhc3_pads[] = { 111 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 115 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 122 }; 123 124 iomux_v3_cfg_t const usdhc4_pads[] = { 125 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 128 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 }; 136 137 iomux_v3_cfg_t const ecspi1_pads[] = { 138 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 139 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 140 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 141 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 142 }; 143 144 static struct i2c_pads_info i2c_pad_info1 = { 145 .scl = { 146 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 147 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 148 .gp = IMX_GPIO_NR(4, 12) 149 }, 150 .sda = { 151 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 152 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 153 .gp = IMX_GPIO_NR(4, 13) 154 } 155 }; 156 157 static void setup_spi(void) 158 { 159 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 160 } 161 162 iomux_v3_cfg_t const pcie_pads[] = { 163 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ 164 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ 165 }; 166 167 static void setup_pcie(void) 168 { 169 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 170 } 171 172 iomux_v3_cfg_t const di0_pads[] = { 173 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ 174 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ 175 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ 176 }; 177 178 static void setup_iomux_uart(void) 179 { 180 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 181 } 182 183 #ifdef CONFIG_FSL_ESDHC 184 struct fsl_esdhc_cfg usdhc_cfg[3] = { 185 {USDHC2_BASE_ADDR}, 186 {USDHC3_BASE_ADDR}, 187 {USDHC4_BASE_ADDR}, 188 }; 189 190 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 191 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 192 193 int board_mmc_getcd(struct mmc *mmc) 194 { 195 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 196 int ret = 0; 197 198 switch (cfg->esdhc_base) { 199 case USDHC2_BASE_ADDR: 200 ret = !gpio_get_value(USDHC2_CD_GPIO); 201 break; 202 case USDHC3_BASE_ADDR: 203 ret = !gpio_get_value(USDHC3_CD_GPIO); 204 break; 205 case USDHC4_BASE_ADDR: 206 ret = 1; /* eMMC/uSDHC4 is always present */ 207 break; 208 } 209 210 return ret; 211 } 212 213 int board_mmc_init(bd_t *bis) 214 { 215 s32 status = 0; 216 int i; 217 218 /* 219 * According to the board_mmc_init() the following map is done: 220 * (U-boot device node) (Physical Port) 221 * mmc0 SD2 222 * mmc1 SD3 223 * mmc2 eMMC 224 */ 225 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 226 switch (i) { 227 case 0: 228 imx_iomux_v3_setup_multiple_pads( 229 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 230 gpio_direction_input(USDHC2_CD_GPIO); 231 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 232 break; 233 case 1: 234 imx_iomux_v3_setup_multiple_pads( 235 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 236 gpio_direction_input(USDHC3_CD_GPIO); 237 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 238 break; 239 case 2: 240 imx_iomux_v3_setup_multiple_pads( 241 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 242 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 243 break; 244 default: 245 printf("Warning: you configured more USDHC controllers" 246 "(%d) then supported by the board (%d)\n", 247 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 248 return status; 249 } 250 251 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 252 } 253 254 return status; 255 } 256 #endif 257 258 int mx6_rgmii_rework(struct phy_device *phydev) 259 { 260 unsigned short val; 261 262 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 263 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 264 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 265 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 266 267 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 268 val &= 0xffe3; 269 val |= 0x18; 270 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 271 272 /* introduce tx clock delay */ 273 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 274 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 275 val |= 0x0100; 276 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 277 278 return 0; 279 } 280 281 int board_phy_config(struct phy_device *phydev) 282 { 283 mx6_rgmii_rework(phydev); 284 285 if (phydev->drv->config) 286 phydev->drv->config(phydev); 287 288 return 0; 289 } 290 291 #if defined(CONFIG_VIDEO_IPUV3) 292 static void disable_lvds(struct display_info_t const *dev) 293 { 294 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 295 296 int reg = readl(&iomux->gpr[2]); 297 298 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | 299 IOMUXC_GPR2_LVDS_CH1_MODE_MASK); 300 301 writel(reg, &iomux->gpr[2]); 302 } 303 304 static void do_enable_hdmi(struct display_info_t const *dev) 305 { 306 disable_lvds(dev); 307 imx_enable_hdmi_phy(); 308 } 309 310 static void enable_lvds(struct display_info_t const *dev) 311 { 312 struct iomuxc *iomux = (struct iomuxc *) 313 IOMUXC_BASE_ADDR; 314 u32 reg = readl(&iomux->gpr[2]); 315 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 316 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; 317 writel(reg, &iomux->gpr[2]); 318 } 319 320 struct display_info_t const displays[] = {{ 321 .bus = -1, 322 .addr = 0, 323 .pixfmt = IPU_PIX_FMT_RGB666, 324 .detect = NULL, 325 .enable = enable_lvds, 326 .mode = { 327 .name = "Hannstar-XGA", 328 .refresh = 60, 329 .xres = 1024, 330 .yres = 768, 331 .pixclock = 15385, 332 .left_margin = 220, 333 .right_margin = 40, 334 .upper_margin = 21, 335 .lower_margin = 7, 336 .hsync_len = 60, 337 .vsync_len = 10, 338 .sync = FB_SYNC_EXT, 339 .vmode = FB_VMODE_NONINTERLACED 340 } }, { 341 .bus = -1, 342 .addr = 0, 343 .pixfmt = IPU_PIX_FMT_RGB24, 344 .detect = detect_hdmi, 345 .enable = do_enable_hdmi, 346 .mode = { 347 .name = "HDMI", 348 .refresh = 60, 349 .xres = 1024, 350 .yres = 768, 351 .pixclock = 15385, 352 .left_margin = 220, 353 .right_margin = 40, 354 .upper_margin = 21, 355 .lower_margin = 7, 356 .hsync_len = 60, 357 .vsync_len = 10, 358 .sync = FB_SYNC_EXT, 359 .vmode = FB_VMODE_NONINTERLACED 360 } } }; 361 size_t display_count = ARRAY_SIZE(displays); 362 363 static void setup_display(void) 364 { 365 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 366 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 367 int reg; 368 369 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ 370 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); 371 372 enable_ipu_clock(); 373 imx_setup_hdmi(); 374 375 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ 376 reg = readl(&mxc_ccm->CCGR3); 377 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 378 writel(reg, &mxc_ccm->CCGR3); 379 380 /* set LDB0, LDB1 clk select to 011/011 */ 381 reg = readl(&mxc_ccm->cs2cdr); 382 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 383 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 384 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 385 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 386 writel(reg, &mxc_ccm->cs2cdr); 387 388 reg = readl(&mxc_ccm->cscmr2); 389 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 390 writel(reg, &mxc_ccm->cscmr2); 391 392 reg = readl(&mxc_ccm->chsccdr); 393 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 394 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 395 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 396 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 397 writel(reg, &mxc_ccm->chsccdr); 398 399 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 400 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW 401 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 402 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 403 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 404 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 405 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 406 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED 407 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; 408 writel(reg, &iomux->gpr[2]); 409 410 reg = readl(&iomux->gpr[3]); 411 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK 412 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 413 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 414 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); 415 writel(reg, &iomux->gpr[3]); 416 } 417 #endif /* CONFIG_VIDEO_IPUV3 */ 418 419 /* 420 * Do not overwrite the console 421 * Use always serial for U-Boot console 422 */ 423 int overwrite_console(void) 424 { 425 return 1; 426 } 427 428 int board_eth_init(bd_t *bis) 429 { 430 setup_iomux_enet(); 431 setup_pcie(); 432 433 return cpu_eth_init(bis); 434 } 435 436 int board_early_init_f(void) 437 { 438 setup_iomux_uart(); 439 #if defined(CONFIG_VIDEO_IPUV3) 440 setup_display(); 441 #endif 442 443 return 0; 444 } 445 446 int board_init(void) 447 { 448 /* address of boot parameters */ 449 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 450 451 #ifdef CONFIG_MXC_SPI 452 setup_spi(); 453 #endif 454 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 455 456 return 0; 457 } 458 459 static int pfuze_init(void) 460 { 461 struct pmic *p; 462 int ret; 463 unsigned int reg; 464 465 ret = power_pfuze100_init(I2C_PMIC); 466 if (ret) 467 return ret; 468 469 p = pmic_get("PFUZE100"); 470 ret = pmic_probe(p); 471 if (ret) 472 return ret; 473 474 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 475 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 476 477 /* Increase VGEN3 from 2.5 to 2.8V */ 478 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); 479 reg &= ~0xf; 480 reg |= 0xa; 481 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); 482 483 /* Increase VGEN5 from 2.8 to 3V */ 484 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 485 reg &= ~0xf; 486 reg |= 0xc; 487 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 488 489 /* Set SW1AB stanby volage to 0.975V */ 490 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); 491 reg &= ~0x3f; 492 reg |= 0x1b; 493 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); 494 495 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 496 pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); 497 reg &= ~0xc0; 498 reg |= 0x40; 499 pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); 500 501 /* Set SW1C standby voltage to 0.975V */ 502 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); 503 reg &= ~0x3f; 504 reg |= 0x1b; 505 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); 506 507 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ 508 pmic_reg_read(p, PFUZE100_SW1CCONF, ®); 509 reg &= ~0xc0; 510 reg |= 0x40; 511 pmic_reg_write(p, PFUZE100_SW1CCONF, reg); 512 513 return 0; 514 } 515 516 #ifdef CONFIG_MXC_SPI 517 int board_spi_cs_gpio(unsigned bus, unsigned cs) 518 { 519 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; 520 } 521 #endif 522 523 #ifdef CONFIG_CMD_BMODE 524 static const struct boot_mode board_boot_modes[] = { 525 /* 4 bit bus width */ 526 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 527 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 528 /* 8 bit bus width */ 529 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 530 {NULL, 0}, 531 }; 532 #endif 533 534 int board_late_init(void) 535 { 536 #ifdef CONFIG_CMD_BMODE 537 add_board_boot_modes(board_boot_modes); 538 #endif 539 pfuze_init(); 540 541 return 0; 542 } 543 544 int checkboard(void) 545 { 546 puts("Board: MX6-SabreSD\n"); 547 return 0; 548 } 549