1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/mxc_i2c.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/video.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <miiphy.h> 22 #include <netdev.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/arch/crm_regs.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <i2c.h> 28 #include <power/pmic.h> 29 #include <power/pfuze100_pmic.h> 30 #include "../common/pfuze.h" 31 #include <asm/arch/mx6-ddr.h> 32 #include <usb.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 38 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 42 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 46 47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 49 50 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 52 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 53 54 #define I2C_PMIC 1 55 56 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 57 58 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) 59 60 int dram_init(void) 61 { 62 gd->ram_size = imx_ddr_size(); 63 return 0; 64 } 65 66 static iomux_v3_cfg_t const uart1_pads[] = { 67 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 68 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 69 }; 70 71 static iomux_v3_cfg_t const enet_pads[] = { 72 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 87 /* AR8031 PHY Reset */ 88 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 89 }; 90 91 static void setup_iomux_enet(void) 92 { 93 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 94 95 /* Reset AR8031 PHY */ 96 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 97 udelay(500); 98 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 99 } 100 101 static iomux_v3_cfg_t const usdhc2_pads[] = { 102 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 111 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 113 }; 114 115 static iomux_v3_cfg_t const usdhc3_pads[] = { 116 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 127 }; 128 129 static iomux_v3_cfg_t const usdhc4_pads[] = { 130 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 }; 141 142 static iomux_v3_cfg_t const ecspi1_pads[] = { 143 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 144 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 145 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 146 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 147 }; 148 149 static iomux_v3_cfg_t const rgb_pads[] = { 150 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 151 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), 152 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), 154 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), 155 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 156 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 157 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 158 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 159 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 160 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 161 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 162 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 163 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), 164 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), 165 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), 166 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), 170 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), 171 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), 172 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), 174 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), 175 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), 178 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), 179 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 180 }; 181 182 static void enable_rgb(struct display_info_t const *dev) 183 { 184 imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); 185 gpio_direction_output(DISP0_PWR_EN, 1); 186 } 187 188 static struct i2c_pads_info i2c_pad_info1 = { 189 .scl = { 190 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 191 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 192 .gp = IMX_GPIO_NR(4, 12) 193 }, 194 .sda = { 195 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 196 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 197 .gp = IMX_GPIO_NR(4, 13) 198 } 199 }; 200 201 static void setup_spi(void) 202 { 203 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 204 } 205 206 iomux_v3_cfg_t const pcie_pads[] = { 207 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ 208 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ 209 }; 210 211 static void setup_pcie(void) 212 { 213 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 214 } 215 216 iomux_v3_cfg_t const di0_pads[] = { 217 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ 218 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ 219 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ 220 }; 221 222 static void setup_iomux_uart(void) 223 { 224 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 225 } 226 227 #ifdef CONFIG_FSL_ESDHC 228 struct fsl_esdhc_cfg usdhc_cfg[3] = { 229 {USDHC2_BASE_ADDR}, 230 {USDHC3_BASE_ADDR}, 231 {USDHC4_BASE_ADDR}, 232 }; 233 234 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 235 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 236 237 int board_mmc_getcd(struct mmc *mmc) 238 { 239 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 240 int ret = 0; 241 242 switch (cfg->esdhc_base) { 243 case USDHC2_BASE_ADDR: 244 ret = !gpio_get_value(USDHC2_CD_GPIO); 245 break; 246 case USDHC3_BASE_ADDR: 247 ret = !gpio_get_value(USDHC3_CD_GPIO); 248 break; 249 case USDHC4_BASE_ADDR: 250 ret = 1; /* eMMC/uSDHC4 is always present */ 251 break; 252 } 253 254 return ret; 255 } 256 257 int board_mmc_init(bd_t *bis) 258 { 259 #ifndef CONFIG_SPL_BUILD 260 int ret; 261 int i; 262 263 /* 264 * According to the board_mmc_init() the following map is done: 265 * (U-boot device node) (Physical Port) 266 * mmc0 SD2 267 * mmc1 SD3 268 * mmc2 eMMC 269 */ 270 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 271 switch (i) { 272 case 0: 273 imx_iomux_v3_setup_multiple_pads( 274 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 275 gpio_direction_input(USDHC2_CD_GPIO); 276 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 277 break; 278 case 1: 279 imx_iomux_v3_setup_multiple_pads( 280 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 281 gpio_direction_input(USDHC3_CD_GPIO); 282 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 283 break; 284 case 2: 285 imx_iomux_v3_setup_multiple_pads( 286 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 287 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 288 break; 289 default: 290 printf("Warning: you configured more USDHC controllers" 291 "(%d) then supported by the board (%d)\n", 292 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 293 return -EINVAL; 294 } 295 296 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 297 if (ret) 298 return ret; 299 } 300 301 return 0; 302 #else 303 struct src *psrc = (struct src *)SRC_BASE_ADDR; 304 unsigned reg = readl(&psrc->sbmr1) >> 11; 305 /* 306 * Upon reading BOOT_CFG register the following map is done: 307 * Bit 11 and 12 of BOOT_CFG register can determine the current 308 * mmc port 309 * 0x1 SD1 310 * 0x2 SD2 311 * 0x3 SD4 312 */ 313 314 switch (reg & 0x3) { 315 case 0x1: 316 imx_iomux_v3_setup_multiple_pads( 317 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 318 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 319 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 320 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 321 break; 322 case 0x2: 323 imx_iomux_v3_setup_multiple_pads( 324 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 325 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 326 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 327 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 328 break; 329 case 0x3: 330 imx_iomux_v3_setup_multiple_pads( 331 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 332 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 333 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 334 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 335 break; 336 } 337 338 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 339 #endif 340 } 341 #endif 342 343 int mx6_rgmii_rework(struct phy_device *phydev) 344 { 345 unsigned short val; 346 347 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 348 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 349 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 350 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 351 352 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 353 val &= 0xffe3; 354 val |= 0x18; 355 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 356 357 /* introduce tx clock delay */ 358 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 359 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 360 val |= 0x0100; 361 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 362 363 return 0; 364 } 365 366 int board_phy_config(struct phy_device *phydev) 367 { 368 mx6_rgmii_rework(phydev); 369 370 if (phydev->drv->config) 371 phydev->drv->config(phydev); 372 373 return 0; 374 } 375 376 #if defined(CONFIG_VIDEO_IPUV3) 377 static void disable_lvds(struct display_info_t const *dev) 378 { 379 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 380 381 int reg = readl(&iomux->gpr[2]); 382 383 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | 384 IOMUXC_GPR2_LVDS_CH1_MODE_MASK); 385 386 writel(reg, &iomux->gpr[2]); 387 } 388 389 static void do_enable_hdmi(struct display_info_t const *dev) 390 { 391 disable_lvds(dev); 392 imx_enable_hdmi_phy(); 393 } 394 395 static void enable_lvds(struct display_info_t const *dev) 396 { 397 struct iomuxc *iomux = (struct iomuxc *) 398 IOMUXC_BASE_ADDR; 399 u32 reg = readl(&iomux->gpr[2]); 400 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 401 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; 402 writel(reg, &iomux->gpr[2]); 403 } 404 405 struct display_info_t const displays[] = {{ 406 .bus = -1, 407 .addr = 0, 408 .pixfmt = IPU_PIX_FMT_RGB666, 409 .detect = NULL, 410 .enable = enable_lvds, 411 .mode = { 412 .name = "Hannstar-XGA", 413 .refresh = 60, 414 .xres = 1024, 415 .yres = 768, 416 .pixclock = 15385, 417 .left_margin = 220, 418 .right_margin = 40, 419 .upper_margin = 21, 420 .lower_margin = 7, 421 .hsync_len = 60, 422 .vsync_len = 10, 423 .sync = FB_SYNC_EXT, 424 .vmode = FB_VMODE_NONINTERLACED 425 } }, { 426 .bus = -1, 427 .addr = 0, 428 .pixfmt = IPU_PIX_FMT_RGB24, 429 .detect = detect_hdmi, 430 .enable = do_enable_hdmi, 431 .mode = { 432 .name = "HDMI", 433 .refresh = 60, 434 .xres = 1024, 435 .yres = 768, 436 .pixclock = 15385, 437 .left_margin = 220, 438 .right_margin = 40, 439 .upper_margin = 21, 440 .lower_margin = 7, 441 .hsync_len = 60, 442 .vsync_len = 10, 443 .sync = FB_SYNC_EXT, 444 .vmode = FB_VMODE_NONINTERLACED 445 } }, { 446 .bus = 0, 447 .addr = 0, 448 .pixfmt = IPU_PIX_FMT_RGB24, 449 .detect = NULL, 450 .enable = enable_rgb, 451 .mode = { 452 .name = "SEIKO-WVGA", 453 .refresh = 60, 454 .xres = 800, 455 .yres = 480, 456 .pixclock = 29850, 457 .left_margin = 89, 458 .right_margin = 164, 459 .upper_margin = 23, 460 .lower_margin = 10, 461 .hsync_len = 10, 462 .vsync_len = 10, 463 .sync = 0, 464 .vmode = FB_VMODE_NONINTERLACED 465 } } }; 466 size_t display_count = ARRAY_SIZE(displays); 467 468 static void setup_display(void) 469 { 470 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 471 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 472 int reg; 473 474 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ 475 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); 476 477 enable_ipu_clock(); 478 imx_setup_hdmi(); 479 480 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ 481 reg = readl(&mxc_ccm->CCGR3); 482 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 483 writel(reg, &mxc_ccm->CCGR3); 484 485 /* set LDB0, LDB1 clk select to 011/011 */ 486 reg = readl(&mxc_ccm->cs2cdr); 487 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 488 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 489 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 490 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 491 writel(reg, &mxc_ccm->cs2cdr); 492 493 reg = readl(&mxc_ccm->cscmr2); 494 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 495 writel(reg, &mxc_ccm->cscmr2); 496 497 reg = readl(&mxc_ccm->chsccdr); 498 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 499 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 500 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 501 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 502 writel(reg, &mxc_ccm->chsccdr); 503 504 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 505 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW 506 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 507 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 508 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 509 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 510 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 511 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED 512 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; 513 writel(reg, &iomux->gpr[2]); 514 515 reg = readl(&iomux->gpr[3]); 516 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK 517 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 518 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 519 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); 520 writel(reg, &iomux->gpr[3]); 521 } 522 #endif /* CONFIG_VIDEO_IPUV3 */ 523 524 /* 525 * Do not overwrite the console 526 * Use always serial for U-Boot console 527 */ 528 int overwrite_console(void) 529 { 530 return 1; 531 } 532 533 int board_eth_init(bd_t *bis) 534 { 535 setup_iomux_enet(); 536 setup_pcie(); 537 538 return cpu_eth_init(bis); 539 } 540 541 #ifdef CONFIG_USB_EHCI_MX6 542 #define USB_OTHERREGS_OFFSET 0x800 543 #define UCTRL_PWR_POL (1 << 9) 544 545 static iomux_v3_cfg_t const usb_otg_pads[] = { 546 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 547 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 548 }; 549 550 static iomux_v3_cfg_t const usb_hc1_pads[] = { 551 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 552 }; 553 554 static void setup_usb(void) 555 { 556 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 557 ARRAY_SIZE(usb_otg_pads)); 558 559 /* 560 * set daisy chain for otg_pin_id on 6q. 561 * for 6dl, this bit is reserved 562 */ 563 imx_iomux_set_gpr_register(1, 13, 1, 0); 564 565 imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, 566 ARRAY_SIZE(usb_hc1_pads)); 567 } 568 569 int board_ehci_hcd_init(int port) 570 { 571 u32 *usbnc_usb_ctrl; 572 573 if (port > 1) 574 return -EINVAL; 575 576 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 577 port * 4); 578 579 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 580 581 return 0; 582 } 583 584 int board_ehci_power(int port, int on) 585 { 586 switch (port) { 587 case 0: 588 break; 589 case 1: 590 if (on) 591 gpio_direction_output(IMX_GPIO_NR(1, 29), 1); 592 else 593 gpio_direction_output(IMX_GPIO_NR(1, 29), 0); 594 break; 595 default: 596 printf("MXC USB port %d not yet supported\n", port); 597 return -EINVAL; 598 } 599 600 return 0; 601 } 602 #endif 603 604 int board_early_init_f(void) 605 { 606 setup_iomux_uart(); 607 #if defined(CONFIG_VIDEO_IPUV3) 608 setup_display(); 609 #endif 610 611 return 0; 612 } 613 614 int board_init(void) 615 { 616 /* address of boot parameters */ 617 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 618 619 #ifdef CONFIG_MXC_SPI 620 setup_spi(); 621 #endif 622 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 623 624 #ifdef CONFIG_USB_EHCI_MX6 625 setup_usb(); 626 #endif 627 628 return 0; 629 } 630 631 int power_init_board(void) 632 { 633 struct pmic *p; 634 unsigned int reg, ret; 635 636 p = pfuze_common_init(I2C_PMIC); 637 if (!p) 638 return -ENODEV; 639 640 ret = pfuze_mode_init(p, APS_PFM); 641 if (ret < 0) 642 return ret; 643 644 /* Increase VGEN3 from 2.5 to 2.8V */ 645 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); 646 reg &= ~LDO_VOL_MASK; 647 reg |= LDOB_2_80V; 648 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); 649 650 /* Increase VGEN5 from 2.8 to 3V */ 651 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 652 reg &= ~LDO_VOL_MASK; 653 reg |= LDOB_3_00V; 654 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 655 656 return 0; 657 } 658 659 #ifdef CONFIG_MXC_SPI 660 int board_spi_cs_gpio(unsigned bus, unsigned cs) 661 { 662 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; 663 } 664 #endif 665 666 #ifdef CONFIG_CMD_BMODE 667 static const struct boot_mode board_boot_modes[] = { 668 /* 4 bit bus width */ 669 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 670 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 671 /* 8 bit bus width */ 672 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 673 {NULL, 0}, 674 }; 675 #endif 676 677 int board_late_init(void) 678 { 679 #ifdef CONFIG_CMD_BMODE 680 add_board_boot_modes(board_boot_modes); 681 #endif 682 return 0; 683 } 684 685 int checkboard(void) 686 { 687 puts("Board: MX6-SabreSD\n"); 688 return 0; 689 } 690 691 #ifdef CONFIG_SPL_BUILD 692 #include <spl.h> 693 #include <libfdt.h> 694 695 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 696 .dram_sdclk_0 = 0x00020030, 697 .dram_sdclk_1 = 0x00020030, 698 .dram_cas = 0x00020030, 699 .dram_ras = 0x00020030, 700 .dram_reset = 0x00020030, 701 .dram_sdcke0 = 0x00003000, 702 .dram_sdcke1 = 0x00003000, 703 .dram_sdba2 = 0x00000000, 704 .dram_sdodt0 = 0x00003030, 705 .dram_sdodt1 = 0x00003030, 706 .dram_sdqs0 = 0x00000030, 707 .dram_sdqs1 = 0x00000030, 708 .dram_sdqs2 = 0x00000030, 709 .dram_sdqs3 = 0x00000030, 710 .dram_sdqs4 = 0x00000030, 711 .dram_sdqs5 = 0x00000030, 712 .dram_sdqs6 = 0x00000030, 713 .dram_sdqs7 = 0x00000030, 714 .dram_dqm0 = 0x00020030, 715 .dram_dqm1 = 0x00020030, 716 .dram_dqm2 = 0x00020030, 717 .dram_dqm3 = 0x00020030, 718 .dram_dqm4 = 0x00020030, 719 .dram_dqm5 = 0x00020030, 720 .dram_dqm6 = 0x00020030, 721 .dram_dqm7 = 0x00020030, 722 }; 723 724 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 725 .grp_ddr_type = 0x000C0000, 726 .grp_ddrmode_ctl = 0x00020000, 727 .grp_ddrpke = 0x00000000, 728 .grp_addds = 0x00000030, 729 .grp_ctlds = 0x00000030, 730 .grp_ddrmode = 0x00020000, 731 .grp_b0ds = 0x00000030, 732 .grp_b1ds = 0x00000030, 733 .grp_b2ds = 0x00000030, 734 .grp_b3ds = 0x00000030, 735 .grp_b4ds = 0x00000030, 736 .grp_b5ds = 0x00000030, 737 .grp_b6ds = 0x00000030, 738 .grp_b7ds = 0x00000030, 739 }; 740 741 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 742 .p0_mpwldectrl0 = 0x001F001F, 743 .p0_mpwldectrl1 = 0x001F001F, 744 .p1_mpwldectrl0 = 0x00440044, 745 .p1_mpwldectrl1 = 0x00440044, 746 .p0_mpdgctrl0 = 0x434B0350, 747 .p0_mpdgctrl1 = 0x034C0359, 748 .p1_mpdgctrl0 = 0x434B0350, 749 .p1_mpdgctrl1 = 0x03650348, 750 .p0_mprddlctl = 0x4436383B, 751 .p1_mprddlctl = 0x39393341, 752 .p0_mpwrdlctl = 0x35373933, 753 .p1_mpwrdlctl = 0x48254A36, 754 }; 755 756 static struct mx6_ddr3_cfg mem_ddr = { 757 .mem_speed = 1600, 758 .density = 4, 759 .width = 64, 760 .banks = 8, 761 .rowaddr = 14, 762 .coladdr = 10, 763 .pagesz = 2, 764 .trcd = 1375, 765 .trcmin = 4875, 766 .trasmin = 3500, 767 }; 768 769 static void ccgr_init(void) 770 { 771 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 772 773 writel(0x00C03F3F, &ccm->CCGR0); 774 writel(0x0030FC03, &ccm->CCGR1); 775 writel(0x0FFFC000, &ccm->CCGR2); 776 writel(0x3FF00000, &ccm->CCGR3); 777 writel(0x00FFF300, &ccm->CCGR4); 778 writel(0x0F0000C3, &ccm->CCGR5); 779 writel(0x000003FF, &ccm->CCGR6); 780 } 781 782 static void gpr_init(void) 783 { 784 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 785 786 /* enable AXI cache for VDOA/VPU/IPU */ 787 writel(0xF00000CF, &iomux->gpr[4]); 788 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 789 writel(0x007F007F, &iomux->gpr[6]); 790 writel(0x007F007F, &iomux->gpr[7]); 791 } 792 793 /* 794 * This section requires the differentiation between iMX6 Sabre boards, but 795 * for now, it will configure only for the mx6q variant. 796 */ 797 static void spl_dram_init(void) 798 { 799 struct mx6_ddr_sysinfo sysinfo = { 800 /* width of data bus:0=16,1=32,2=64 */ 801 .dsize = mem_ddr.width/32, 802 /* config for full 4GB range so that get_mem_size() works */ 803 .cs_density = 32, /* 32Gb per CS */ 804 /* single chip select */ 805 .ncs = 1, 806 .cs1_mirror = 0, 807 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 808 #ifdef RTT_NOM_120OHM 809 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 810 #else 811 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 812 #endif 813 .walat = 1, /* Write additional latency */ 814 .ralat = 5, /* Read additional latency */ 815 .mif3_mode = 3, /* Command prediction working mode */ 816 .bi_on = 1, /* Bank interleaving enabled */ 817 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 818 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 819 }; 820 821 mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 822 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 823 } 824 825 void board_init_f(ulong dummy) 826 { 827 /* setup AIPS and disable watchdog */ 828 arch_cpu_init(); 829 830 ccgr_init(); 831 gpr_init(); 832 833 /* iomux and setup of i2c */ 834 board_early_init_f(); 835 836 /* setup GP timer */ 837 timer_init(); 838 839 /* UART clocks enabled and gd valid - init serial console */ 840 preloader_console_init(); 841 842 /* DDR initialization */ 843 spl_dram_init(); 844 845 /* Clear the BSS. */ 846 memset(__bss_start, 0, __bss_end - __bss_start); 847 848 /* load/boot image from boot device */ 849 board_init_r(NULL, 0); 850 } 851 852 void reset_cpu(ulong addr) 853 { 854 } 855 #endif 856