1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/mxc_i2c.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/video.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <miiphy.h> 22 #include <netdev.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/arch/crm_regs.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <i2c.h> 28 #include <power/pmic.h> 29 #include <power/pfuze100_pmic.h> 30 #include "../common/pfuze.h" 31 #include <asm/arch/mx6-ddr.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 45 46 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 47 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 48 49 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 51 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 52 53 #define I2C_PMIC 1 54 55 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 56 57 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) 58 59 int dram_init(void) 60 { 61 gd->ram_size = imx_ddr_size(); 62 return 0; 63 } 64 65 static iomux_v3_cfg_t const uart1_pads[] = { 66 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 67 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 68 }; 69 70 static iomux_v3_cfg_t const enet_pads[] = { 71 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 72 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 /* AR8031 PHY Reset */ 87 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 88 }; 89 90 static void setup_iomux_enet(void) 91 { 92 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 93 94 /* Reset AR8031 PHY */ 95 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 96 udelay(500); 97 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 98 } 99 100 static iomux_v3_cfg_t const usdhc2_pads[] = { 101 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 111 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 112 }; 113 114 static iomux_v3_cfg_t const usdhc3_pads[] = { 115 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 126 }; 127 128 static iomux_v3_cfg_t const usdhc4_pads[] = { 129 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 }; 140 141 static iomux_v3_cfg_t const ecspi1_pads[] = { 142 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 143 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 144 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 145 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 146 }; 147 148 static iomux_v3_cfg_t const rgb_pads[] = { 149 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 150 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), 151 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), 152 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), 154 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 155 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 156 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 157 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 158 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 159 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 160 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 161 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 162 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), 163 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), 164 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), 165 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), 166 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), 170 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), 171 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), 172 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), 174 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), 175 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), 178 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 179 }; 180 181 static void enable_rgb(struct display_info_t const *dev) 182 { 183 imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); 184 gpio_direction_output(DISP0_PWR_EN, 1); 185 } 186 187 static struct i2c_pads_info i2c_pad_info1 = { 188 .scl = { 189 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 190 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 191 .gp = IMX_GPIO_NR(4, 12) 192 }, 193 .sda = { 194 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 195 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 196 .gp = IMX_GPIO_NR(4, 13) 197 } 198 }; 199 200 static void setup_spi(void) 201 { 202 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 203 } 204 205 iomux_v3_cfg_t const pcie_pads[] = { 206 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ 207 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ 208 }; 209 210 static void setup_pcie(void) 211 { 212 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 213 } 214 215 iomux_v3_cfg_t const di0_pads[] = { 216 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ 217 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ 218 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ 219 }; 220 221 static void setup_iomux_uart(void) 222 { 223 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 224 } 225 226 #ifdef CONFIG_FSL_ESDHC 227 struct fsl_esdhc_cfg usdhc_cfg[3] = { 228 {USDHC2_BASE_ADDR}, 229 {USDHC3_BASE_ADDR}, 230 {USDHC4_BASE_ADDR}, 231 }; 232 233 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 234 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 235 236 int board_mmc_getcd(struct mmc *mmc) 237 { 238 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 239 int ret = 0; 240 241 switch (cfg->esdhc_base) { 242 case USDHC2_BASE_ADDR: 243 ret = !gpio_get_value(USDHC2_CD_GPIO); 244 break; 245 case USDHC3_BASE_ADDR: 246 ret = !gpio_get_value(USDHC3_CD_GPIO); 247 break; 248 case USDHC4_BASE_ADDR: 249 ret = 1; /* eMMC/uSDHC4 is always present */ 250 break; 251 } 252 253 return ret; 254 } 255 256 int board_mmc_init(bd_t *bis) 257 { 258 #ifndef CONFIG_SPL_BUILD 259 int ret; 260 int i; 261 262 /* 263 * According to the board_mmc_init() the following map is done: 264 * (U-boot device node) (Physical Port) 265 * mmc0 SD2 266 * mmc1 SD3 267 * mmc2 eMMC 268 */ 269 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 270 switch (i) { 271 case 0: 272 imx_iomux_v3_setup_multiple_pads( 273 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 274 gpio_direction_input(USDHC2_CD_GPIO); 275 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 276 break; 277 case 1: 278 imx_iomux_v3_setup_multiple_pads( 279 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 280 gpio_direction_input(USDHC3_CD_GPIO); 281 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 282 break; 283 case 2: 284 imx_iomux_v3_setup_multiple_pads( 285 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 286 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 287 break; 288 default: 289 printf("Warning: you configured more USDHC controllers" 290 "(%d) then supported by the board (%d)\n", 291 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 292 return -EINVAL; 293 } 294 295 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 296 if (ret) 297 return ret; 298 } 299 300 return 0; 301 #else 302 struct src *psrc = (struct src *)SRC_BASE_ADDR; 303 unsigned reg = readl(&psrc->sbmr1) >> 11; 304 /* 305 * Upon reading BOOT_CFG register the following map is done: 306 * Bit 11 and 12 of BOOT_CFG register can determine the current 307 * mmc port 308 * 0x1 SD1 309 * 0x2 SD2 310 * 0x3 SD4 311 */ 312 313 switch (reg & 0x3) { 314 case 0x1: 315 imx_iomux_v3_setup_multiple_pads( 316 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 317 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 318 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 319 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 320 break; 321 case 0x2: 322 imx_iomux_v3_setup_multiple_pads( 323 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 324 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 325 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 326 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 327 break; 328 case 0x3: 329 imx_iomux_v3_setup_multiple_pads( 330 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 331 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 332 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 333 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 334 break; 335 } 336 337 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 338 #endif 339 } 340 #endif 341 342 int mx6_rgmii_rework(struct phy_device *phydev) 343 { 344 unsigned short val; 345 346 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 347 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 348 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 349 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 350 351 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 352 val &= 0xffe3; 353 val |= 0x18; 354 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 355 356 /* introduce tx clock delay */ 357 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 358 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 359 val |= 0x0100; 360 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 361 362 return 0; 363 } 364 365 int board_phy_config(struct phy_device *phydev) 366 { 367 mx6_rgmii_rework(phydev); 368 369 if (phydev->drv->config) 370 phydev->drv->config(phydev); 371 372 return 0; 373 } 374 375 #if defined(CONFIG_VIDEO_IPUV3) 376 static void disable_lvds(struct display_info_t const *dev) 377 { 378 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 379 380 int reg = readl(&iomux->gpr[2]); 381 382 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | 383 IOMUXC_GPR2_LVDS_CH1_MODE_MASK); 384 385 writel(reg, &iomux->gpr[2]); 386 } 387 388 static void do_enable_hdmi(struct display_info_t const *dev) 389 { 390 disable_lvds(dev); 391 imx_enable_hdmi_phy(); 392 } 393 394 static void enable_lvds(struct display_info_t const *dev) 395 { 396 struct iomuxc *iomux = (struct iomuxc *) 397 IOMUXC_BASE_ADDR; 398 u32 reg = readl(&iomux->gpr[2]); 399 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 400 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; 401 writel(reg, &iomux->gpr[2]); 402 } 403 404 struct display_info_t const displays[] = {{ 405 .bus = -1, 406 .addr = 0, 407 .pixfmt = IPU_PIX_FMT_RGB666, 408 .detect = NULL, 409 .enable = enable_lvds, 410 .mode = { 411 .name = "Hannstar-XGA", 412 .refresh = 60, 413 .xres = 1024, 414 .yres = 768, 415 .pixclock = 15385, 416 .left_margin = 220, 417 .right_margin = 40, 418 .upper_margin = 21, 419 .lower_margin = 7, 420 .hsync_len = 60, 421 .vsync_len = 10, 422 .sync = FB_SYNC_EXT, 423 .vmode = FB_VMODE_NONINTERLACED 424 } }, { 425 .bus = -1, 426 .addr = 0, 427 .pixfmt = IPU_PIX_FMT_RGB24, 428 .detect = detect_hdmi, 429 .enable = do_enable_hdmi, 430 .mode = { 431 .name = "HDMI", 432 .refresh = 60, 433 .xres = 1024, 434 .yres = 768, 435 .pixclock = 15385, 436 .left_margin = 220, 437 .right_margin = 40, 438 .upper_margin = 21, 439 .lower_margin = 7, 440 .hsync_len = 60, 441 .vsync_len = 10, 442 .sync = FB_SYNC_EXT, 443 .vmode = FB_VMODE_NONINTERLACED 444 } }, { 445 .bus = 0, 446 .addr = 0, 447 .pixfmt = IPU_PIX_FMT_RGB24, 448 .detect = NULL, 449 .enable = enable_rgb, 450 .mode = { 451 .name = "SEIKO-WVGA", 452 .refresh = 60, 453 .xres = 800, 454 .yres = 480, 455 .pixclock = 29850, 456 .left_margin = 89, 457 .right_margin = 164, 458 .upper_margin = 23, 459 .lower_margin = 10, 460 .hsync_len = 10, 461 .vsync_len = 10, 462 .sync = 0, 463 .vmode = FB_VMODE_NONINTERLACED 464 } } }; 465 size_t display_count = ARRAY_SIZE(displays); 466 467 static void setup_display(void) 468 { 469 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 470 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 471 int reg; 472 473 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ 474 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); 475 476 enable_ipu_clock(); 477 imx_setup_hdmi(); 478 479 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ 480 reg = readl(&mxc_ccm->CCGR3); 481 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 482 writel(reg, &mxc_ccm->CCGR3); 483 484 /* set LDB0, LDB1 clk select to 011/011 */ 485 reg = readl(&mxc_ccm->cs2cdr); 486 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 487 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 488 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 489 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 490 writel(reg, &mxc_ccm->cs2cdr); 491 492 reg = readl(&mxc_ccm->cscmr2); 493 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 494 writel(reg, &mxc_ccm->cscmr2); 495 496 reg = readl(&mxc_ccm->chsccdr); 497 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 498 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 499 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 500 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 501 writel(reg, &mxc_ccm->chsccdr); 502 503 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 504 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW 505 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 506 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 507 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 508 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 509 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 510 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED 511 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; 512 writel(reg, &iomux->gpr[2]); 513 514 reg = readl(&iomux->gpr[3]); 515 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK 516 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 517 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 518 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); 519 writel(reg, &iomux->gpr[3]); 520 } 521 #endif /* CONFIG_VIDEO_IPUV3 */ 522 523 /* 524 * Do not overwrite the console 525 * Use always serial for U-Boot console 526 */ 527 int overwrite_console(void) 528 { 529 return 1; 530 } 531 532 int board_eth_init(bd_t *bis) 533 { 534 setup_iomux_enet(); 535 setup_pcie(); 536 537 return cpu_eth_init(bis); 538 } 539 540 int board_early_init_f(void) 541 { 542 setup_iomux_uart(); 543 #if defined(CONFIG_VIDEO_IPUV3) 544 setup_display(); 545 #endif 546 547 return 0; 548 } 549 550 int board_init(void) 551 { 552 /* address of boot parameters */ 553 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 554 555 #ifdef CONFIG_MXC_SPI 556 setup_spi(); 557 #endif 558 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 559 560 return 0; 561 } 562 563 int power_init_board(void) 564 { 565 struct pmic *p; 566 unsigned int reg; 567 568 p = pfuze_common_init(I2C_PMIC); 569 if (!p) 570 return -ENODEV; 571 572 /* Increase VGEN3 from 2.5 to 2.8V */ 573 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); 574 reg &= ~LDO_VOL_MASK; 575 reg |= LDOB_2_80V; 576 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); 577 578 /* Increase VGEN5 from 2.8 to 3V */ 579 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 580 reg &= ~LDO_VOL_MASK; 581 reg |= LDOB_3_00V; 582 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 583 584 return 0; 585 } 586 587 #ifdef CONFIG_MXC_SPI 588 int board_spi_cs_gpio(unsigned bus, unsigned cs) 589 { 590 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; 591 } 592 #endif 593 594 #ifdef CONFIG_CMD_BMODE 595 static const struct boot_mode board_boot_modes[] = { 596 /* 4 bit bus width */ 597 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 598 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 599 /* 8 bit bus width */ 600 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 601 {NULL, 0}, 602 }; 603 #endif 604 605 int board_late_init(void) 606 { 607 #ifdef CONFIG_CMD_BMODE 608 add_board_boot_modes(board_boot_modes); 609 #endif 610 return 0; 611 } 612 613 int checkboard(void) 614 { 615 puts("Board: MX6-SabreSD\n"); 616 return 0; 617 } 618 619 #ifdef CONFIG_SPL_BUILD 620 #include <spl.h> 621 #include <libfdt.h> 622 623 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 624 .dram_sdclk_0 = 0x00020030, 625 .dram_sdclk_1 = 0x00020030, 626 .dram_cas = 0x00020030, 627 .dram_ras = 0x00020030, 628 .dram_reset = 0x00020030, 629 .dram_sdcke0 = 0x00003000, 630 .dram_sdcke1 = 0x00003000, 631 .dram_sdba2 = 0x00000000, 632 .dram_sdodt0 = 0x00003030, 633 .dram_sdodt1 = 0x00003030, 634 .dram_sdqs0 = 0x00000030, 635 .dram_sdqs1 = 0x00000030, 636 .dram_sdqs2 = 0x00000030, 637 .dram_sdqs3 = 0x00000030, 638 .dram_sdqs4 = 0x00000030, 639 .dram_sdqs5 = 0x00000030, 640 .dram_sdqs6 = 0x00000030, 641 .dram_sdqs7 = 0x00000030, 642 .dram_dqm0 = 0x00020030, 643 .dram_dqm1 = 0x00020030, 644 .dram_dqm2 = 0x00020030, 645 .dram_dqm3 = 0x00020030, 646 .dram_dqm4 = 0x00020030, 647 .dram_dqm5 = 0x00020030, 648 .dram_dqm6 = 0x00020030, 649 .dram_dqm7 = 0x00020030, 650 }; 651 652 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 653 .grp_ddr_type = 0x000C0000, 654 .grp_ddrmode_ctl = 0x00020000, 655 .grp_ddrpke = 0x00000000, 656 .grp_addds = 0x00000030, 657 .grp_ctlds = 0x00000030, 658 .grp_ddrmode = 0x00020000, 659 .grp_b0ds = 0x00000030, 660 .grp_b1ds = 0x00000030, 661 .grp_b2ds = 0x00000030, 662 .grp_b3ds = 0x00000030, 663 .grp_b4ds = 0x00000030, 664 .grp_b5ds = 0x00000030, 665 .grp_b6ds = 0x00000030, 666 .grp_b7ds = 0x00000030, 667 }; 668 669 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 670 .p0_mpwldectrl0 = 0x001F001F, 671 .p0_mpwldectrl1 = 0x001F001F, 672 .p1_mpwldectrl0 = 0x00440044, 673 .p1_mpwldectrl1 = 0x00440044, 674 .p0_mpdgctrl0 = 0x434B0350, 675 .p0_mpdgctrl1 = 0x034C0359, 676 .p1_mpdgctrl0 = 0x434B0350, 677 .p1_mpdgctrl1 = 0x03650348, 678 .p0_mprddlctl = 0x4436383B, 679 .p1_mprddlctl = 0x39393341, 680 .p0_mpwrdlctl = 0x35373933, 681 .p1_mpwrdlctl = 0x48254A36, 682 }; 683 684 static struct mx6_ddr3_cfg mem_ddr = { 685 .mem_speed = 1600, 686 .density = 4, 687 .width = 64, 688 .banks = 8, 689 .rowaddr = 14, 690 .coladdr = 10, 691 .pagesz = 2, 692 .trcd = 1375, 693 .trcmin = 4875, 694 .trasmin = 3500, 695 }; 696 697 static void ccgr_init(void) 698 { 699 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 700 701 writel(0x00C03F3F, &ccm->CCGR0); 702 writel(0x0030FC03, &ccm->CCGR1); 703 writel(0x0FFFC000, &ccm->CCGR2); 704 writel(0x3FF00000, &ccm->CCGR3); 705 writel(0x00FFF300, &ccm->CCGR4); 706 writel(0x0F0000C3, &ccm->CCGR5); 707 writel(0x000003FF, &ccm->CCGR6); 708 } 709 710 static void gpr_init(void) 711 { 712 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 713 714 /* enable AXI cache for VDOA/VPU/IPU */ 715 writel(0xF00000CF, &iomux->gpr[4]); 716 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 717 writel(0x007F007F, &iomux->gpr[6]); 718 writel(0x007F007F, &iomux->gpr[7]); 719 } 720 721 /* 722 * This section requires the differentiation between iMX6 Sabre boards, but 723 * for now, it will configure only for the mx6q variant. 724 */ 725 static void spl_dram_init(void) 726 { 727 struct mx6_ddr_sysinfo sysinfo = { 728 /* width of data bus:0=16,1=32,2=64 */ 729 .dsize = mem_ddr.width/32, 730 /* config for full 4GB range so that get_mem_size() works */ 731 .cs_density = 32, /* 32Gb per CS */ 732 /* single chip select */ 733 .ncs = 1, 734 .cs1_mirror = 0, 735 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 736 #ifdef RTT_NOM_120OHM 737 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 738 #else 739 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 740 #endif 741 .walat = 1, /* Write additional latency */ 742 .ralat = 5, /* Read additional latency */ 743 .mif3_mode = 3, /* Command prediction working mode */ 744 .bi_on = 1, /* Bank interleaving enabled */ 745 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 746 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 747 }; 748 749 mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 750 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 751 } 752 753 void board_init_f(ulong dummy) 754 { 755 /* setup AIPS and disable watchdog */ 756 arch_cpu_init(); 757 758 ccgr_init(); 759 gpr_init(); 760 761 /* iomux and setup of i2c */ 762 board_early_init_f(); 763 764 /* setup GP timer */ 765 timer_init(); 766 767 /* UART clocks enabled and gd valid - init serial console */ 768 preloader_console_init(); 769 770 /* DDR initialization */ 771 spl_dram_init(); 772 773 /* Clear the BSS. */ 774 memset(__bss_start, 0, __bss_end - __bss_start); 775 776 /* load/boot image from boot device */ 777 board_init_r(NULL, 0); 778 } 779 780 void reset_cpu(ulong addr) 781 { 782 } 783 #endif 784