1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/mxc_i2c.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/video.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <miiphy.h> 22 #include <netdev.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/arch/crm_regs.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <i2c.h> 28 #include <power/pmic.h> 29 #include <power/pfuze100_pmic.h> 30 #include "../common/pfuze.h" 31 #include <asm/arch/mx6-ddr.h> 32 #include <usb.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 38 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 42 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 46 47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 49 50 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 52 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 53 54 #define I2C_PMIC 1 55 56 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 57 58 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) 59 60 int dram_init(void) 61 { 62 gd->ram_size = imx_ddr_size(); 63 return 0; 64 } 65 66 static iomux_v3_cfg_t const uart1_pads[] = { 67 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 68 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 69 }; 70 71 static iomux_v3_cfg_t const enet_pads[] = { 72 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 87 /* AR8031 PHY Reset */ 88 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 89 }; 90 91 static void setup_iomux_enet(void) 92 { 93 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 94 95 /* Reset AR8031 PHY */ 96 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 97 mdelay(10); 98 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 99 udelay(100); 100 } 101 102 static iomux_v3_cfg_t const usdhc2_pads[] = { 103 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 111 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 114 }; 115 116 static iomux_v3_cfg_t const usdhc3_pads[] = { 117 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 128 }; 129 130 static iomux_v3_cfg_t const usdhc4_pads[] = { 131 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 }; 142 143 static iomux_v3_cfg_t const ecspi1_pads[] = { 144 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 145 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 146 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 147 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 148 }; 149 150 static iomux_v3_cfg_t const rgb_pads[] = { 151 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 152 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), 154 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), 155 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), 156 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 157 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 158 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 159 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 160 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 161 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 162 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 163 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 164 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), 165 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), 166 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), 170 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), 171 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), 172 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), 174 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), 175 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), 178 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), 179 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), 180 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 181 }; 182 183 static void enable_rgb(struct display_info_t const *dev) 184 { 185 imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); 186 gpio_direction_output(DISP0_PWR_EN, 1); 187 } 188 189 static struct i2c_pads_info i2c_pad_info1 = { 190 .scl = { 191 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 192 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 193 .gp = IMX_GPIO_NR(4, 12) 194 }, 195 .sda = { 196 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 197 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 198 .gp = IMX_GPIO_NR(4, 13) 199 } 200 }; 201 202 static void setup_spi(void) 203 { 204 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 205 } 206 207 iomux_v3_cfg_t const pcie_pads[] = { 208 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ 209 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ 210 }; 211 212 static void setup_pcie(void) 213 { 214 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 215 } 216 217 iomux_v3_cfg_t const di0_pads[] = { 218 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ 219 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ 220 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ 221 }; 222 223 static void setup_iomux_uart(void) 224 { 225 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 226 } 227 228 #ifdef CONFIG_FSL_ESDHC 229 struct fsl_esdhc_cfg usdhc_cfg[3] = { 230 {USDHC2_BASE_ADDR}, 231 {USDHC3_BASE_ADDR}, 232 {USDHC4_BASE_ADDR}, 233 }; 234 235 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 236 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 237 238 int board_mmc_getcd(struct mmc *mmc) 239 { 240 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 241 int ret = 0; 242 243 switch (cfg->esdhc_base) { 244 case USDHC2_BASE_ADDR: 245 ret = !gpio_get_value(USDHC2_CD_GPIO); 246 break; 247 case USDHC3_BASE_ADDR: 248 ret = !gpio_get_value(USDHC3_CD_GPIO); 249 break; 250 case USDHC4_BASE_ADDR: 251 ret = 1; /* eMMC/uSDHC4 is always present */ 252 break; 253 } 254 255 return ret; 256 } 257 258 int board_mmc_init(bd_t *bis) 259 { 260 #ifndef CONFIG_SPL_BUILD 261 int ret; 262 int i; 263 264 /* 265 * According to the board_mmc_init() the following map is done: 266 * (U-boot device node) (Physical Port) 267 * mmc0 SD2 268 * mmc1 SD3 269 * mmc2 eMMC 270 */ 271 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 272 switch (i) { 273 case 0: 274 imx_iomux_v3_setup_multiple_pads( 275 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 276 gpio_direction_input(USDHC2_CD_GPIO); 277 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 278 break; 279 case 1: 280 imx_iomux_v3_setup_multiple_pads( 281 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 282 gpio_direction_input(USDHC3_CD_GPIO); 283 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 284 break; 285 case 2: 286 imx_iomux_v3_setup_multiple_pads( 287 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 288 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 289 break; 290 default: 291 printf("Warning: you configured more USDHC controllers" 292 "(%d) then supported by the board (%d)\n", 293 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 294 return -EINVAL; 295 } 296 297 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 298 if (ret) 299 return ret; 300 } 301 302 return 0; 303 #else 304 struct src *psrc = (struct src *)SRC_BASE_ADDR; 305 unsigned reg = readl(&psrc->sbmr1) >> 11; 306 /* 307 * Upon reading BOOT_CFG register the following map is done: 308 * Bit 11 and 12 of BOOT_CFG register can determine the current 309 * mmc port 310 * 0x1 SD1 311 * 0x2 SD2 312 * 0x3 SD4 313 */ 314 315 switch (reg & 0x3) { 316 case 0x1: 317 imx_iomux_v3_setup_multiple_pads( 318 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 319 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 320 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 321 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 322 break; 323 case 0x2: 324 imx_iomux_v3_setup_multiple_pads( 325 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 326 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 327 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 328 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 329 break; 330 case 0x3: 331 imx_iomux_v3_setup_multiple_pads( 332 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 333 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 334 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 335 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 336 break; 337 } 338 339 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 340 #endif 341 } 342 #endif 343 344 #if defined(CONFIG_VIDEO_IPUV3) 345 static void disable_lvds(struct display_info_t const *dev) 346 { 347 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 348 349 int reg = readl(&iomux->gpr[2]); 350 351 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | 352 IOMUXC_GPR2_LVDS_CH1_MODE_MASK); 353 354 writel(reg, &iomux->gpr[2]); 355 } 356 357 static void do_enable_hdmi(struct display_info_t const *dev) 358 { 359 disable_lvds(dev); 360 imx_enable_hdmi_phy(); 361 } 362 363 static void enable_lvds(struct display_info_t const *dev) 364 { 365 struct iomuxc *iomux = (struct iomuxc *) 366 IOMUXC_BASE_ADDR; 367 u32 reg = readl(&iomux->gpr[2]); 368 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 369 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; 370 writel(reg, &iomux->gpr[2]); 371 } 372 373 struct display_info_t const displays[] = {{ 374 .bus = -1, 375 .addr = 0, 376 .pixfmt = IPU_PIX_FMT_RGB666, 377 .detect = NULL, 378 .enable = enable_lvds, 379 .mode = { 380 .name = "Hannstar-XGA", 381 .refresh = 60, 382 .xres = 1024, 383 .yres = 768, 384 .pixclock = 15385, 385 .left_margin = 220, 386 .right_margin = 40, 387 .upper_margin = 21, 388 .lower_margin = 7, 389 .hsync_len = 60, 390 .vsync_len = 10, 391 .sync = FB_SYNC_EXT, 392 .vmode = FB_VMODE_NONINTERLACED 393 } }, { 394 .bus = -1, 395 .addr = 0, 396 .pixfmt = IPU_PIX_FMT_RGB24, 397 .detect = detect_hdmi, 398 .enable = do_enable_hdmi, 399 .mode = { 400 .name = "HDMI", 401 .refresh = 60, 402 .xres = 1024, 403 .yres = 768, 404 .pixclock = 15385, 405 .left_margin = 220, 406 .right_margin = 40, 407 .upper_margin = 21, 408 .lower_margin = 7, 409 .hsync_len = 60, 410 .vsync_len = 10, 411 .sync = FB_SYNC_EXT, 412 .vmode = FB_VMODE_NONINTERLACED 413 } }, { 414 .bus = 0, 415 .addr = 0, 416 .pixfmt = IPU_PIX_FMT_RGB24, 417 .detect = NULL, 418 .enable = enable_rgb, 419 .mode = { 420 .name = "SEIKO-WVGA", 421 .refresh = 60, 422 .xres = 800, 423 .yres = 480, 424 .pixclock = 29850, 425 .left_margin = 89, 426 .right_margin = 164, 427 .upper_margin = 23, 428 .lower_margin = 10, 429 .hsync_len = 10, 430 .vsync_len = 10, 431 .sync = 0, 432 .vmode = FB_VMODE_NONINTERLACED 433 } } }; 434 size_t display_count = ARRAY_SIZE(displays); 435 436 static void setup_display(void) 437 { 438 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 439 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 440 int reg; 441 442 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ 443 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); 444 445 enable_ipu_clock(); 446 imx_setup_hdmi(); 447 448 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ 449 reg = readl(&mxc_ccm->CCGR3); 450 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 451 writel(reg, &mxc_ccm->CCGR3); 452 453 /* set LDB0, LDB1 clk select to 011/011 */ 454 reg = readl(&mxc_ccm->cs2cdr); 455 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 456 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 457 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 458 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 459 writel(reg, &mxc_ccm->cs2cdr); 460 461 reg = readl(&mxc_ccm->cscmr2); 462 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 463 writel(reg, &mxc_ccm->cscmr2); 464 465 reg = readl(&mxc_ccm->chsccdr); 466 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 467 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 468 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 469 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 470 writel(reg, &mxc_ccm->chsccdr); 471 472 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 473 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW 474 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 475 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 476 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 477 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 478 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 479 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED 480 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; 481 writel(reg, &iomux->gpr[2]); 482 483 reg = readl(&iomux->gpr[3]); 484 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK 485 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 486 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 487 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); 488 writel(reg, &iomux->gpr[3]); 489 } 490 #endif /* CONFIG_VIDEO_IPUV3 */ 491 492 /* 493 * Do not overwrite the console 494 * Use always serial for U-Boot console 495 */ 496 int overwrite_console(void) 497 { 498 return 1; 499 } 500 501 int board_eth_init(bd_t *bis) 502 { 503 setup_iomux_enet(); 504 setup_pcie(); 505 506 return cpu_eth_init(bis); 507 } 508 509 #ifdef CONFIG_USB_EHCI_MX6 510 #define USB_OTHERREGS_OFFSET 0x800 511 #define UCTRL_PWR_POL (1 << 9) 512 513 static iomux_v3_cfg_t const usb_otg_pads[] = { 514 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 515 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 516 }; 517 518 static iomux_v3_cfg_t const usb_hc1_pads[] = { 519 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 520 }; 521 522 static void setup_usb(void) 523 { 524 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 525 ARRAY_SIZE(usb_otg_pads)); 526 527 /* 528 * set daisy chain for otg_pin_id on 6q. 529 * for 6dl, this bit is reserved 530 */ 531 imx_iomux_set_gpr_register(1, 13, 1, 0); 532 533 imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, 534 ARRAY_SIZE(usb_hc1_pads)); 535 } 536 537 int board_ehci_hcd_init(int port) 538 { 539 u32 *usbnc_usb_ctrl; 540 541 if (port > 1) 542 return -EINVAL; 543 544 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 545 port * 4); 546 547 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 548 549 return 0; 550 } 551 552 int board_ehci_power(int port, int on) 553 { 554 switch (port) { 555 case 0: 556 break; 557 case 1: 558 if (on) 559 gpio_direction_output(IMX_GPIO_NR(1, 29), 1); 560 else 561 gpio_direction_output(IMX_GPIO_NR(1, 29), 0); 562 break; 563 default: 564 printf("MXC USB port %d not yet supported\n", port); 565 return -EINVAL; 566 } 567 568 return 0; 569 } 570 #endif 571 572 int board_early_init_f(void) 573 { 574 setup_iomux_uart(); 575 #if defined(CONFIG_VIDEO_IPUV3) 576 setup_display(); 577 #endif 578 579 return 0; 580 } 581 582 int board_init(void) 583 { 584 /* address of boot parameters */ 585 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 586 587 #ifdef CONFIG_MXC_SPI 588 setup_spi(); 589 #endif 590 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 591 592 #ifdef CONFIG_USB_EHCI_MX6 593 setup_usb(); 594 #endif 595 596 return 0; 597 } 598 599 int power_init_board(void) 600 { 601 struct pmic *p; 602 unsigned int reg; 603 int ret; 604 605 p = pfuze_common_init(I2C_PMIC); 606 if (!p) 607 return -ENODEV; 608 609 ret = pfuze_mode_init(p, APS_PFM); 610 if (ret < 0) 611 return ret; 612 613 /* Increase VGEN3 from 2.5 to 2.8V */ 614 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); 615 reg &= ~LDO_VOL_MASK; 616 reg |= LDOB_2_80V; 617 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); 618 619 /* Increase VGEN5 from 2.8 to 3V */ 620 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); 621 reg &= ~LDO_VOL_MASK; 622 reg |= LDOB_3_00V; 623 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); 624 625 return 0; 626 } 627 628 #ifdef CONFIG_MXC_SPI 629 int board_spi_cs_gpio(unsigned bus, unsigned cs) 630 { 631 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; 632 } 633 #endif 634 635 #ifdef CONFIG_CMD_BMODE 636 static const struct boot_mode board_boot_modes[] = { 637 /* 4 bit bus width */ 638 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 639 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 640 /* 8 bit bus width */ 641 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 642 {NULL, 0}, 643 }; 644 #endif 645 646 int board_late_init(void) 647 { 648 #ifdef CONFIG_CMD_BMODE 649 add_board_boot_modes(board_boot_modes); 650 #endif 651 652 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 653 setenv("board_name", "SABRESD"); 654 655 if (is_mx6dqp()) 656 setenv("board_rev", "MX6QP"); 657 else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 658 setenv("board_rev", "MX6Q"); 659 else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) 660 setenv("board_rev", "MX6DL"); 661 #endif 662 663 return 0; 664 } 665 666 int checkboard(void) 667 { 668 puts("Board: MX6-SabreSD\n"); 669 return 0; 670 } 671 672 #ifdef CONFIG_SPL_BUILD 673 #include <spl.h> 674 #include <libfdt.h> 675 676 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 677 .dram_sdclk_0 = 0x00020030, 678 .dram_sdclk_1 = 0x00020030, 679 .dram_cas = 0x00020030, 680 .dram_ras = 0x00020030, 681 .dram_reset = 0x00020030, 682 .dram_sdcke0 = 0x00003000, 683 .dram_sdcke1 = 0x00003000, 684 .dram_sdba2 = 0x00000000, 685 .dram_sdodt0 = 0x00003030, 686 .dram_sdodt1 = 0x00003030, 687 .dram_sdqs0 = 0x00000030, 688 .dram_sdqs1 = 0x00000030, 689 .dram_sdqs2 = 0x00000030, 690 .dram_sdqs3 = 0x00000030, 691 .dram_sdqs4 = 0x00000030, 692 .dram_sdqs5 = 0x00000030, 693 .dram_sdqs6 = 0x00000030, 694 .dram_sdqs7 = 0x00000030, 695 .dram_dqm0 = 0x00020030, 696 .dram_dqm1 = 0x00020030, 697 .dram_dqm2 = 0x00020030, 698 .dram_dqm3 = 0x00020030, 699 .dram_dqm4 = 0x00020030, 700 .dram_dqm5 = 0x00020030, 701 .dram_dqm6 = 0x00020030, 702 .dram_dqm7 = 0x00020030, 703 }; 704 705 const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = { 706 .dram_sdclk_0 = 0x00000030, 707 .dram_sdclk_1 = 0x00000030, 708 .dram_cas = 0x00000030, 709 .dram_ras = 0x00000030, 710 .dram_reset = 0x00000030, 711 .dram_sdcke0 = 0x00003000, 712 .dram_sdcke1 = 0x00003000, 713 .dram_sdba2 = 0x00000000, 714 .dram_sdodt0 = 0x00003030, 715 .dram_sdodt1 = 0x00003030, 716 .dram_sdqs0 = 0x00000030, 717 .dram_sdqs1 = 0x00000030, 718 .dram_sdqs2 = 0x00000030, 719 .dram_sdqs3 = 0x00000030, 720 .dram_sdqs4 = 0x00000030, 721 .dram_sdqs5 = 0x00000030, 722 .dram_sdqs6 = 0x00000030, 723 .dram_sdqs7 = 0x00000030, 724 .dram_dqm0 = 0x00000030, 725 .dram_dqm1 = 0x00000030, 726 .dram_dqm2 = 0x00000030, 727 .dram_dqm3 = 0x00000030, 728 .dram_dqm4 = 0x00000030, 729 .dram_dqm5 = 0x00000030, 730 .dram_dqm6 = 0x00000030, 731 .dram_dqm7 = 0x00000030, 732 }; 733 734 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 735 .grp_ddr_type = 0x000C0000, 736 .grp_ddrmode_ctl = 0x00020000, 737 .grp_ddrpke = 0x00000000, 738 .grp_addds = 0x00000030, 739 .grp_ctlds = 0x00000030, 740 .grp_ddrmode = 0x00020000, 741 .grp_b0ds = 0x00000030, 742 .grp_b1ds = 0x00000030, 743 .grp_b2ds = 0x00000030, 744 .grp_b3ds = 0x00000030, 745 .grp_b4ds = 0x00000030, 746 .grp_b5ds = 0x00000030, 747 .grp_b6ds = 0x00000030, 748 .grp_b7ds = 0x00000030, 749 }; 750 751 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 752 .p0_mpwldectrl0 = 0x001F001F, 753 .p0_mpwldectrl1 = 0x001F001F, 754 .p1_mpwldectrl0 = 0x00440044, 755 .p1_mpwldectrl1 = 0x00440044, 756 .p0_mpdgctrl0 = 0x434B0350, 757 .p0_mpdgctrl1 = 0x034C0359, 758 .p1_mpdgctrl0 = 0x434B0350, 759 .p1_mpdgctrl1 = 0x03650348, 760 .p0_mprddlctl = 0x4436383B, 761 .p1_mprddlctl = 0x39393341, 762 .p0_mpwrdlctl = 0x35373933, 763 .p1_mpwrdlctl = 0x48254A36, 764 }; 765 766 const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = { 767 .p0_mpwldectrl0 = 0x001B001E, 768 .p0_mpwldectrl1 = 0x002E0029, 769 .p1_mpwldectrl0 = 0x001B002A, 770 .p1_mpwldectrl1 = 0x0019002C, 771 .p0_mpdgctrl0 = 0x43240334, 772 .p0_mpdgctrl1 = 0x0324031A, 773 .p1_mpdgctrl0 = 0x43340344, 774 .p1_mpdgctrl1 = 0x03280276, 775 .p0_mprddlctl = 0x44383A3E, 776 .p1_mprddlctl = 0x3C3C3846, 777 .p0_mpwrdlctl = 0x2E303230, 778 .p1_mpwrdlctl = 0x38283E34, 779 }; 780 781 /* MT41K128M16JT-125 */ 782 static struct mx6_ddr3_cfg mem_ddr = { 783 .mem_speed = 1600, 784 .density = 2, 785 .width = 16, 786 .banks = 8, 787 .rowaddr = 14, 788 .coladdr = 10, 789 .pagesz = 2, 790 .trcd = 1375, 791 .trcmin = 4875, 792 .trasmin = 3500, 793 }; 794 795 static void ccgr_init(void) 796 { 797 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 798 799 writel(0x00C03F3F, &ccm->CCGR0); 800 writel(0x0030FC03, &ccm->CCGR1); 801 writel(0x0FFFC000, &ccm->CCGR2); 802 writel(0x3FF00000, &ccm->CCGR3); 803 writel(0x00FFF300, &ccm->CCGR4); 804 writel(0x0F0000C3, &ccm->CCGR5); 805 writel(0x000003FF, &ccm->CCGR6); 806 } 807 808 static void gpr_init(void) 809 { 810 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 811 812 /* enable AXI cache for VDOA/VPU/IPU */ 813 writel(0xF00000CF, &iomux->gpr[4]); 814 if (is_mx6dqp()) { 815 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ 816 writel(0x007F007F, &iomux->gpr[6]); 817 writel(0x007F007F, &iomux->gpr[7]); 818 } else { 819 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 820 writel(0x007F007F, &iomux->gpr[6]); 821 writel(0x007F007F, &iomux->gpr[7]); 822 } 823 } 824 825 /* 826 * This section requires the differentiation between iMX6 Sabre boards, but 827 * for now, it will configure only for the mx6q variant. 828 */ 829 static void spl_dram_init(void) 830 { 831 struct mx6_ddr_sysinfo sysinfo = { 832 /* width of data bus:0=16,1=32,2=64 */ 833 .dsize = 2, 834 /* config for full 4GB range so that get_mem_size() works */ 835 .cs_density = 32, /* 32Gb per CS */ 836 /* single chip select */ 837 .ncs = 1, 838 .cs1_mirror = 0, 839 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 840 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 841 .walat = 1, /* Write additional latency */ 842 .ralat = 5, /* Read additional latency */ 843 .mif3_mode = 3, /* Command prediction working mode */ 844 .bi_on = 1, /* Bank interleaving enabled */ 845 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 846 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 847 .ddr_type = DDR_TYPE_DDR3, 848 }; 849 850 if (is_mx6dqp()) { 851 mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); 852 mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); 853 } else { 854 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 855 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 856 } 857 } 858 859 void board_init_f(ulong dummy) 860 { 861 /* setup AIPS and disable watchdog */ 862 arch_cpu_init(); 863 864 ccgr_init(); 865 gpr_init(); 866 867 /* iomux and setup of i2c */ 868 board_early_init_f(); 869 870 /* setup GP timer */ 871 timer_init(); 872 873 /* UART clocks enabled and gd valid - init serial console */ 874 preloader_console_init(); 875 876 /* DDR initialization */ 877 spl_dram_init(); 878 879 /* Clear the BSS. */ 880 memset(__bss_start, 0, __bss_end - __bss_start); 881 882 /* load/boot image from boot device */ 883 board_init_r(NULL, 0); 884 } 885 #endif 886