1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/boot_mode.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 25 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 26 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 27 28 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 29 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 30 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31 32 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 34 35 int dram_init(void) 36 { 37 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 38 39 return 0; 40 } 41 42 iomux_v3_cfg_t const uart1_pads[] = { 43 MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 44 MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 45 }; 46 47 iomux_v3_cfg_t const enet_pads[] = { 48 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 49 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 50 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 51 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 52 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 53 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 54 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 55 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 56 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 57 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 58 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 59 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 60 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 61 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 62 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 63 /* AR8031 PHY Reset */ 64 MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), 65 }; 66 67 static void setup_iomux_enet(void) 68 { 69 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 70 71 /* Reset AR8031 PHY */ 72 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 73 udelay(500); 74 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 75 } 76 77 iomux_v3_cfg_t const usdhc2_pads[] = { 78 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 89 }; 90 91 iomux_v3_cfg_t const usdhc3_pads[] = { 92 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 95 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 103 }; 104 105 iomux_v3_cfg_t const usdhc4_pads[] = { 106 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 111 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112 MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113 MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114 MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 115 MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116 }; 117 118 static void setup_iomux_uart(void) 119 { 120 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 121 } 122 123 #ifdef CONFIG_FSL_ESDHC 124 struct fsl_esdhc_cfg usdhc_cfg[3] = { 125 {USDHC2_BASE_ADDR}, 126 {USDHC3_BASE_ADDR}, 127 {USDHC4_BASE_ADDR}, 128 }; 129 130 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 131 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 132 133 int board_mmc_getcd(struct mmc *mmc) 134 { 135 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 136 int ret = 0; 137 138 switch (cfg->esdhc_base) { 139 case USDHC2_BASE_ADDR: 140 ret = !gpio_get_value(USDHC2_CD_GPIO); 141 break; 142 case USDHC3_BASE_ADDR: 143 ret = !gpio_get_value(USDHC3_CD_GPIO); 144 break; 145 case USDHC4_BASE_ADDR: 146 ret = 1; /* eMMC/uSDHC4 is always present */ 147 break; 148 } 149 150 return ret; 151 } 152 153 int board_mmc_init(bd_t *bis) 154 { 155 s32 status = 0; 156 int i; 157 158 /* 159 * According to the board_mmc_init() the following map is done: 160 * (U-boot device node) (Physical Port) 161 * mmc0 SD2 162 * mmc1 SD3 163 * mmc2 eMMC 164 */ 165 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 166 switch (i) { 167 case 0: 168 imx_iomux_v3_setup_multiple_pads( 169 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 170 gpio_direction_input(USDHC2_CD_GPIO); 171 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 172 break; 173 case 1: 174 imx_iomux_v3_setup_multiple_pads( 175 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 176 gpio_direction_input(USDHC3_CD_GPIO); 177 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 178 break; 179 case 2: 180 imx_iomux_v3_setup_multiple_pads( 181 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 182 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 183 break; 184 default: 185 printf("Warning: you configured more USDHC controllers" 186 "(%d) then supported by the board (%d)\n", 187 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 188 return status; 189 } 190 191 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 192 } 193 194 return status; 195 } 196 #endif 197 198 int mx6_rgmii_rework(struct phy_device *phydev) 199 { 200 unsigned short val; 201 202 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 203 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 204 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 205 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 206 207 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 208 val &= 0xffe3; 209 val |= 0x18; 210 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 211 212 /* introduce tx clock delay */ 213 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 214 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 215 val |= 0x0100; 216 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 217 218 return 0; 219 } 220 221 int board_phy_config(struct phy_device *phydev) 222 { 223 mx6_rgmii_rework(phydev); 224 225 if (phydev->drv->config) 226 phydev->drv->config(phydev); 227 228 return 0; 229 } 230 231 int board_eth_init(bd_t *bis) 232 { 233 int ret; 234 235 setup_iomux_enet(); 236 237 ret = cpu_eth_init(bis); 238 if (ret) 239 printf("FEC MXC: %s:failed\n", __func__); 240 241 return 0; 242 } 243 244 int board_early_init_f(void) 245 { 246 setup_iomux_uart(); 247 248 return 0; 249 } 250 251 int board_init(void) 252 { 253 /* address of boot parameters */ 254 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 255 256 return 0; 257 } 258 259 #ifdef CONFIG_CMD_BMODE 260 static const struct boot_mode board_boot_modes[] = { 261 /* 4 bit bus width */ 262 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 263 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 264 /* 8 bit bus width */ 265 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 266 {NULL, 0}, 267 }; 268 #endif 269 270 int board_late_init(void) 271 { 272 #ifdef CONFIG_CMD_BMODE 273 add_board_boot_modes(board_boot_modes); 274 #endif 275 276 return 0; 277 } 278 279 int checkboard(void) 280 { 281 puts("Board: MX6-SabreSD\n"); 282 return 0; 283 } 284