1 /*
2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <linux/errno.h>
16 #include <asm/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/spi.h>
21 #include <mmc.h>
22 #include <fsl_esdhc.h>
23 #include <miiphy.h>
24 #include <netdev.h>
25 #include <asm/arch/sys_proto.h>
26 #include <i2c.h>
27 #include <input.h>
28 #include <asm/arch/mxc_hdmi.h>
29 #include <asm/mach-imx/video.h>
30 #include <asm/arch/crm_regs.h>
31 #include <pca953x.h>
32 #include <power/pmic.h>
33 #include <power/pfuze100_pmic.h>
34 #include "../common/pfuze.h"
35 
36 DECLARE_GLOBAL_DATA_PTR;
37 
38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
39 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
40 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
41 
42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
43 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
44 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
45 
46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
47 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48 
49 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
50 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
51 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
52 
53 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
54 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
55 			PAD_CTL_SRE_FAST)
56 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
57 
58 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
59 
60 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
61 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
62 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
63 
64 #define I2C_PMIC	1
65 
66 int dram_init(void)
67 {
68 	gd->ram_size = imx_ddr_size();
69 
70 	return 0;
71 }
72 
73 static iomux_v3_cfg_t const uart4_pads[] = {
74 	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
75 	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
76 };
77 
78 static iomux_v3_cfg_t const enet_pads[] = {
79 	IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 	IOMUX_PADS(PAD_KEY_COL2__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
92 	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
94 };
95 
96 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
97 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
98 	.scl = {
99 		.i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
100 		.gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
101 		.gp = IMX_GPIO_NR(2, 30)
102 	},
103 	.sda = {
104 		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
105 		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
106 		.gp = IMX_GPIO_NR(4, 13)
107 	}
108 };
109 
110 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
111 	.scl = {
112 		.i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
113 		.gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
114 		.gp = IMX_GPIO_NR(2, 30)
115 	},
116 	.sda = {
117 		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
118 		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
119 		.gp = IMX_GPIO_NR(4, 13)
120 	}
121 };
122 
123 #ifndef CONFIG_SYS_FLASH_CFI
124 /*
125  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
126  * Compass Sensor, Accelerometer, Res Touch
127  */
128 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
129 	.scl = {
130 		.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
131 		.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
132 		.gp = IMX_GPIO_NR(1, 3)
133 	},
134 	.sda = {
135 		.i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
136 		.gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
137 		.gp = IMX_GPIO_NR(3, 18)
138 	}
139 };
140 
141 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
142 	.scl = {
143 		.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
144 		.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
145 		.gp = IMX_GPIO_NR(1, 3)
146 	},
147 	.sda = {
148 		.i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
149 		.gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
150 		.gp = IMX_GPIO_NR(3, 18)
151 	}
152 };
153 #endif
154 
155 static iomux_v3_cfg_t const i2c3_pads[] = {
156 	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL)),
157 };
158 
159 static iomux_v3_cfg_t const port_exp[] = {
160 	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
161 };
162 
163 /*Define for building port exp gpio, pin starts from 0*/
164 #define PORTEXP_IO_NR(chip, pin) \
165 	((chip << 5) + pin)
166 
167 /*Get the chip addr from a ioexp gpio*/
168 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
169 	(gpio_nr >> 5)
170 
171 /*Get the pin number from a ioexp gpio*/
172 #define PORTEXP_IO_TO_PIN(gpio_nr) \
173 	(gpio_nr & 0x1f)
174 
175 static int port_exp_direction_output(unsigned gpio, int value)
176 {
177 	int ret;
178 
179 	i2c_set_bus_num(2);
180 	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
181 	if (ret)
182 		return ret;
183 
184 	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
185 		(1 << PORTEXP_IO_TO_PIN(gpio)),
186 		(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
187 
188 	if (ret)
189 		return ret;
190 
191 	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
192 		(1 << PORTEXP_IO_TO_PIN(gpio)),
193 		(value << PORTEXP_IO_TO_PIN(gpio)));
194 
195 	if (ret)
196 		return ret;
197 
198 	return 0;
199 }
200 
201 #ifdef CONFIG_MTD_NOR_FLASH
202 static iomux_v3_cfg_t const eimnor_pads[] = {
203 	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
204 	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
205 	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
206 	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
207 	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
208 	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
209 	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
210 	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
211 	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
212 	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
213 	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
214 	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
215 	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
216 	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
217 	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
218 	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
219 	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
220 	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
221 	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
222 	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
223 	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
224 	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
225 	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
226 	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
227 	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
228 	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
229 	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
230 	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
231 	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
232 	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
233 	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
234 	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
235 	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
236 	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
237 	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
238 	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
239 	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
240 	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
241 	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
242 	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
243 	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B		| MUX_PAD_CTRL(NO_PAD_CTRL)),
244 	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
245 	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
246 };
247 
248 static void eimnor_cs_setup(void)
249 {
250 	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
251 
252 	writel(0x00020181, &weim_regs->cs0gcr1);
253 	writel(0x00000001, &weim_regs->cs0gcr2);
254 	writel(0x0a020000, &weim_regs->cs0rcr1);
255 	writel(0x0000c000, &weim_regs->cs0rcr2);
256 	writel(0x0804a240, &weim_regs->cs0wcr1);
257 	writel(0x00000120, &weim_regs->wcr);
258 
259 	set_chipselect_size(CS0_128);
260 }
261 
262 static void eim_clk_setup(void)
263 {
264 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
265 	int cscmr1, ccgr6;
266 
267 
268 	/* Turn off EIM clock */
269 	ccgr6 = readl(&imx_ccm->CCGR6);
270 	ccgr6 &= ~(0x3 << 10);
271 	writel(ccgr6, &imx_ccm->CCGR6);
272 
273 	/*
274 	 * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
275 	 * and aclk_eim_slow_podf = 01 --> divide by 2
276 	 * so that we can have EIM at the maximum clock of 132MHz
277 	 */
278 	cscmr1 = readl(&imx_ccm->cscmr1);
279 	cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
280 		    MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
281 	cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
282 	writel(cscmr1, &imx_ccm->cscmr1);
283 
284 	/* Turn on EIM clock */
285 	ccgr6 |= (0x3 << 10);
286 	writel(ccgr6, &imx_ccm->CCGR6);
287 }
288 
289 static void setup_iomux_eimnor(void)
290 {
291 	SETUP_IOMUX_PADS(eimnor_pads);
292 
293 	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
294 
295 	eimnor_cs_setup();
296 }
297 #endif
298 
299 static void setup_iomux_enet(void)
300 {
301 	SETUP_IOMUX_PADS(enet_pads);
302 }
303 
304 static iomux_v3_cfg_t const usdhc3_pads[] = {
305 	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
306 	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
307 	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
308 	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
309 	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
310 	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
311 	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
312 	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
313 	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
314 	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
315 	IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
316 	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
317 };
318 
319 static void setup_iomux_uart(void)
320 {
321 	SETUP_IOMUX_PADS(uart4_pads);
322 }
323 
324 #ifdef CONFIG_FSL_ESDHC
325 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
326 	{USDHC3_BASE_ADDR},
327 };
328 
329 int board_mmc_getcd(struct mmc *mmc)
330 {
331 	gpio_direction_input(IMX_GPIO_NR(6, 15));
332 	return !gpio_get_value(IMX_GPIO_NR(6, 15));
333 }
334 
335 int board_mmc_init(bd_t *bis)
336 {
337 	SETUP_IOMUX_PADS(usdhc3_pads);
338 
339 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
340 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
341 }
342 #endif
343 
344 #ifdef CONFIG_NAND_MXS
345 static iomux_v3_cfg_t gpmi_pads[] = {
346 	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
347 	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
348 	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
349 	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
350 	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
351 	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
352 	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
353 	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
354 	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
355 	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
356 	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
357 	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
358 	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
359 	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
360 	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
361 	IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS	| MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
362 };
363 
364 static void setup_gpmi_nand(void)
365 {
366 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
367 
368 	/* config gpmi nand iomux */
369 	SETUP_IOMUX_PADS(gpmi_pads);
370 
371 	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
372 			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
373 			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
374 
375 	/* enable apbh clock gating */
376 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
377 }
378 #endif
379 
380 static void setup_fec(void)
381 {
382 	if (is_mx6dqp()) {
383 		/*
384 		 * select ENET MAC0 TX clock from PLL
385 		 */
386 		imx_iomux_set_gpr_register(5, 9, 1, 1);
387 		enable_fec_anatop_clock(0, ENET_125MHZ);
388 	}
389 
390 	setup_iomux_enet();
391 }
392 
393 int board_eth_init(bd_t *bis)
394 {
395 	setup_fec();
396 
397 	return cpu_eth_init(bis);
398 }
399 
400 u32 get_board_rev(void)
401 {
402 	int rev = nxp_board_rev();
403 
404 	return (get_cpu_rev() & ~(0xF << 8)) | rev;
405 }
406 
407 static int ar8031_phy_fixup(struct phy_device *phydev)
408 {
409 	unsigned short val;
410 
411 	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
412 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
413 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
414 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
415 
416 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
417 	val &= 0xffe3;
418 	val |= 0x18;
419 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
420 
421 	/* introduce tx clock delay */
422 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
423 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
424 	val |= 0x0100;
425 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
426 
427 	return 0;
428 }
429 
430 int board_phy_config(struct phy_device *phydev)
431 {
432 	ar8031_phy_fixup(phydev);
433 
434 	if (phydev->drv->config)
435 		phydev->drv->config(phydev);
436 
437 	return 0;
438 }
439 
440 #if defined(CONFIG_VIDEO_IPUV3)
441 static void disable_lvds(struct display_info_t const *dev)
442 {
443 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
444 
445 	clrbits_le32(&iomux->gpr[2],
446 		     IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
447 		     IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
448 }
449 
450 static void do_enable_hdmi(struct display_info_t const *dev)
451 {
452 	disable_lvds(dev);
453 	imx_enable_hdmi_phy();
454 }
455 
456 struct display_info_t const displays[] = {{
457 	.bus	= -1,
458 	.addr	= 0,
459 	.pixfmt	= IPU_PIX_FMT_RGB666,
460 	.detect	= NULL,
461 	.enable	= NULL,
462 	.mode	= {
463 		.name           = "Hannstar-XGA",
464 		.refresh        = 60,
465 		.xres           = 1024,
466 		.yres           = 768,
467 		.pixclock       = 15385,
468 		.left_margin    = 220,
469 		.right_margin   = 40,
470 		.upper_margin   = 21,
471 		.lower_margin   = 7,
472 		.hsync_len      = 60,
473 		.vsync_len      = 10,
474 		.sync           = FB_SYNC_EXT,
475 		.vmode          = FB_VMODE_NONINTERLACED
476 } }, {
477 	.bus	= -1,
478 	.addr	= 0,
479 	.pixfmt	= IPU_PIX_FMT_RGB24,
480 	.detect	= detect_hdmi,
481 	.enable	= do_enable_hdmi,
482 	.mode	= {
483 		.name           = "HDMI",
484 		.refresh        = 60,
485 		.xres           = 1024,
486 		.yres           = 768,
487 		.pixclock       = 15385,
488 		.left_margin    = 220,
489 		.right_margin   = 40,
490 		.upper_margin   = 21,
491 		.lower_margin   = 7,
492 		.hsync_len      = 60,
493 		.vsync_len      = 10,
494 		.sync           = FB_SYNC_EXT,
495 		.vmode          = FB_VMODE_NONINTERLACED,
496 } } };
497 size_t display_count = ARRAY_SIZE(displays);
498 
499 iomux_v3_cfg_t const backlight_pads[] = {
500 	IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
501 };
502 
503 static void setup_iomux_backlight(void)
504 {
505 	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
506 	SETUP_IOMUX_PADS(backlight_pads);
507 }
508 
509 static void setup_display(void)
510 {
511 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
512 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
513 	int reg;
514 
515 	setup_iomux_backlight();
516 	enable_ipu_clock();
517 	imx_setup_hdmi();
518 
519 	/* Turn on LDB_DI0 and LDB_DI1 clocks */
520 	reg = readl(&mxc_ccm->CCGR3);
521 	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
522 	writel(reg, &mxc_ccm->CCGR3);
523 
524 	/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
525 	reg = readl(&mxc_ccm->cs2cdr);
526 	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
527 		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
528 	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
529 	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
530 	writel(reg, &mxc_ccm->cs2cdr);
531 
532 	reg = readl(&mxc_ccm->cscmr2);
533 	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
534 	writel(reg, &mxc_ccm->cscmr2);
535 
536 	reg = readl(&mxc_ccm->chsccdr);
537 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
538 		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
539 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
540 		MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
541 	writel(reg, &mxc_ccm->chsccdr);
542 
543 	reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
544 	      IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
545 	      IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
546 	      IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
547 	      IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
548 	      IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
549 	      IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
550 	      IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
551 	writel(reg, &iomux->gpr[2]);
552 
553 	reg = readl(&iomux->gpr[3]);
554 	reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
555 		 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
556 	reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
557 		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
558 	       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
559 		IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
560 	writel(reg, &iomux->gpr[3]);
561 }
562 #endif /* CONFIG_VIDEO_IPUV3 */
563 
564 /*
565  * Do not overwrite the console
566  * Use always serial for U-Boot console
567  */
568 int overwrite_console(void)
569 {
570 	return 1;
571 }
572 
573 int board_early_init_f(void)
574 {
575 	setup_iomux_uart();
576 
577 #ifdef CONFIG_NAND_MXS
578 	setup_gpmi_nand();
579 #endif
580 
581 #ifdef CONFIG_MTD_NOR_FLASH
582 	eim_clk_setup();
583 #endif
584 	return 0;
585 }
586 
587 int board_init(void)
588 {
589 	/* address of boot parameters */
590 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
591 
592 	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
593 	if (is_mx6dq() || is_mx6dqp())
594 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
595 	else
596 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
597 	/* I2C 3 Steer */
598 	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
599 	SETUP_IOMUX_PADS(i2c3_pads);
600 #ifndef CONFIG_SYS_FLASH_CFI
601 	if (is_mx6dq() || is_mx6dqp())
602 		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
603 	else
604 		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
605 #endif
606 	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
607 	SETUP_IOMUX_PADS(port_exp);
608 
609 #ifdef CONFIG_VIDEO_IPUV3
610 	setup_display();
611 #endif
612 
613 #ifdef CONFIG_MTD_NOR_FLASH
614 	setup_iomux_eimnor();
615 #endif
616 	return 0;
617 }
618 
619 #ifdef CONFIG_MXC_SPI
620 int board_spi_cs_gpio(unsigned bus, unsigned cs)
621 {
622 	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
623 }
624 #endif
625 
626 int power_init_board(void)
627 {
628 	struct pmic *p;
629 	unsigned int value;
630 
631 	p = pfuze_common_init(I2C_PMIC);
632 	if (!p)
633 		return -ENODEV;
634 
635 	if (is_mx6dqp()) {
636 		/* set SW2 staby volatage 0.975V*/
637 		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
638 		value &= ~0x3f;
639 		value |= 0x17;
640 		pmic_reg_write(p, PFUZE100_SW2STBY, value);
641 	}
642 
643 	return pfuze_mode_init(p, APS_PFM);
644 }
645 
646 #ifdef CONFIG_CMD_BMODE
647 static const struct boot_mode board_boot_modes[] = {
648 	/* 4 bit bus width */
649 	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
650 	{NULL,   0},
651 };
652 #endif
653 
654 int board_late_init(void)
655 {
656 #ifdef CONFIG_CMD_BMODE
657 	add_board_boot_modes(board_boot_modes);
658 #endif
659 
660 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
661 	env_set("board_name", "SABREAUTO");
662 
663 	if (is_mx6dqp())
664 		env_set("board_rev", "MX6QP");
665 	else if (is_mx6dq())
666 		env_set("board_rev", "MX6Q");
667 	else if (is_mx6sdl())
668 		env_set("board_rev", "MX6DL");
669 #endif
670 
671 	return 0;
672 }
673 
674 int checkboard(void)
675 {
676 	printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
677 
678 	return 0;
679 }
680 
681 #ifdef CONFIG_USB_EHCI_MX6
682 #define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
683 #define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
684 
685 iomux_v3_cfg_t const usb_otg_pads[] = {
686 	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
687 };
688 
689 int board_ehci_hcd_init(int port)
690 {
691 	switch (port) {
692 	case 0:
693 		SETUP_IOMUX_PADS(usb_otg_pads);
694 
695 		/*
696 		  * Set daisy chain for otg_pin_id on 6q.
697 		 *  For 6dl, this bit is reserved.
698 		 */
699 		imx_iomux_set_gpr_register(1, 13, 1, 0);
700 		break;
701 	case 1:
702 		break;
703 	default:
704 		printf("MXC USB port %d not yet supported\n", port);
705 		return -EINVAL;
706 	}
707 	return 0;
708 }
709 
710 int board_ehci_power(int port, int on)
711 {
712 	switch (port) {
713 	case 0:
714 		if (on)
715 			port_exp_direction_output(USB_OTG_PWR, 1);
716 		else
717 			port_exp_direction_output(USB_OTG_PWR, 0);
718 		break;
719 	case 1:
720 		if (on)
721 			port_exp_direction_output(USB_HOST1_PWR, 1);
722 		else
723 			port_exp_direction_output(USB_HOST1_PWR, 0);
724 		break;
725 	default:
726 		printf("MXC USB port %d not yet supported\n", port);
727 		return -EINVAL;
728 	}
729 
730 	return 0;
731 }
732 #endif
733 
734 #ifdef CONFIG_SPL_BUILD
735 #include <asm/arch/mx6-ddr.h>
736 #include <spl.h>
737 #include <linux/libfdt.h>
738 
739 #ifdef CONFIG_SPL_OS_BOOT
740 int spl_start_uboot(void)
741 {
742 	return 0;
743 }
744 #endif
745 
746 static void ccgr_init(void)
747 {
748 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
749 
750 	writel(0x00C03F3F, &ccm->CCGR0);
751 	writel(0x0030FC03, &ccm->CCGR1);
752 	writel(0x0FFFC000, &ccm->CCGR2);
753 	writel(0x3FF00000, &ccm->CCGR3);
754 	writel(0x00FFF300, &ccm->CCGR4);
755 	writel(0x0F0000C3, &ccm->CCGR5);
756 	writel(0x000003FF, &ccm->CCGR6);
757 }
758 
759 static int mx6q_dcd_table[] = {
760 	0x020e0798, 0x000C0000,
761 	0x020e0758, 0x00000000,
762 	0x020e0588, 0x00000030,
763 	0x020e0594, 0x00000030,
764 	0x020e056c, 0x00000030,
765 	0x020e0578, 0x00000030,
766 	0x020e074c, 0x00000030,
767 	0x020e057c, 0x00000030,
768 	0x020e058c, 0x00000000,
769 	0x020e059c, 0x00000030,
770 	0x020e05a0, 0x00000030,
771 	0x020e078c, 0x00000030,
772 	0x020e0750, 0x00020000,
773 	0x020e05a8, 0x00000028,
774 	0x020e05b0, 0x00000028,
775 	0x020e0524, 0x00000028,
776 	0x020e051c, 0x00000028,
777 	0x020e0518, 0x00000028,
778 	0x020e050c, 0x00000028,
779 	0x020e05b8, 0x00000028,
780 	0x020e05c0, 0x00000028,
781 	0x020e0774, 0x00020000,
782 	0x020e0784, 0x00000028,
783 	0x020e0788, 0x00000028,
784 	0x020e0794, 0x00000028,
785 	0x020e079c, 0x00000028,
786 	0x020e07a0, 0x00000028,
787 	0x020e07a4, 0x00000028,
788 	0x020e07a8, 0x00000028,
789 	0x020e0748, 0x00000028,
790 	0x020e05ac, 0x00000028,
791 	0x020e05b4, 0x00000028,
792 	0x020e0528, 0x00000028,
793 	0x020e0520, 0x00000028,
794 	0x020e0514, 0x00000028,
795 	0x020e0510, 0x00000028,
796 	0x020e05bc, 0x00000028,
797 	0x020e05c4, 0x00000028,
798 	0x021b0800, 0xa1390003,
799 	0x021b080c, 0x001F001F,
800 	0x021b0810, 0x001F001F,
801 	0x021b480c, 0x001F001F,
802 	0x021b4810, 0x001F001F,
803 	0x021b083c, 0x43260335,
804 	0x021b0840, 0x031A030B,
805 	0x021b483c, 0x4323033B,
806 	0x021b4840, 0x0323026F,
807 	0x021b0848, 0x483D4545,
808 	0x021b4848, 0x44433E48,
809 	0x021b0850, 0x41444840,
810 	0x021b4850, 0x4835483E,
811 	0x021b081c, 0x33333333,
812 	0x021b0820, 0x33333333,
813 	0x021b0824, 0x33333333,
814 	0x021b0828, 0x33333333,
815 	0x021b481c, 0x33333333,
816 	0x021b4820, 0x33333333,
817 	0x021b4824, 0x33333333,
818 	0x021b4828, 0x33333333,
819 	0x021b08b8, 0x00000800,
820 	0x021b48b8, 0x00000800,
821 	0x021b0004, 0x00020036,
822 	0x021b0008, 0x09444040,
823 	0x021b000c, 0x8A8F7955,
824 	0x021b0010, 0xFF328F64,
825 	0x021b0014, 0x01FF00DB,
826 	0x021b0018, 0x00001740,
827 	0x021b001c, 0x00008000,
828 	0x021b002c, 0x000026d2,
829 	0x021b0030, 0x008F1023,
830 	0x021b0040, 0x00000047,
831 	0x021b0000, 0x841A0000,
832 	0x021b001c, 0x04088032,
833 	0x021b001c, 0x00008033,
834 	0x021b001c, 0x00048031,
835 	0x021b001c, 0x09408030,
836 	0x021b001c, 0x04008040,
837 	0x021b0020, 0x00005800,
838 	0x021b0818, 0x00011117,
839 	0x021b4818, 0x00011117,
840 	0x021b0004, 0x00025576,
841 	0x021b0404, 0x00011006,
842 	0x021b001c, 0x00000000,
843 	0x020c4068, 0x00C03F3F,
844 	0x020c406c, 0x0030FC03,
845 	0x020c4070, 0x0FFFC000,
846 	0x020c4074, 0x3FF00000,
847 	0x020c4078, 0xFFFFF300,
848 	0x020c407c, 0x0F0000F3,
849 	0x020c4080, 0x00000FFF,
850 	0x020e0010, 0xF00000CF,
851 	0x020e0018, 0x007F007F,
852 	0x020e001c, 0x007F007F,
853 };
854 
855 static int mx6qp_dcd_table[] = {
856 	0x020e0798, 0x000C0000,
857 	0x020e0758, 0x00000000,
858 	0x020e0588, 0x00000030,
859 	0x020e0594, 0x00000030,
860 	0x020e056c, 0x00000030,
861 	0x020e0578, 0x00000030,
862 	0x020e074c, 0x00000030,
863 	0x020e057c, 0x00000030,
864 	0x020e058c, 0x00000000,
865 	0x020e059c, 0x00000030,
866 	0x020e05a0, 0x00000030,
867 	0x020e078c, 0x00000030,
868 	0x020e0750, 0x00020000,
869 	0x020e05a8, 0x00000030,
870 	0x020e05b0, 0x00000030,
871 	0x020e0524, 0x00000030,
872 	0x020e051c, 0x00000030,
873 	0x020e0518, 0x00000030,
874 	0x020e050c, 0x00000030,
875 	0x020e05b8, 0x00000030,
876 	0x020e05c0, 0x00000030,
877 	0x020e0774, 0x00020000,
878 	0x020e0784, 0x00000030,
879 	0x020e0788, 0x00000030,
880 	0x020e0794, 0x00000030,
881 	0x020e079c, 0x00000030,
882 	0x020e07a0, 0x00000030,
883 	0x020e07a4, 0x00000030,
884 	0x020e07a8, 0x00000030,
885 	0x020e0748, 0x00000030,
886 	0x020e05ac, 0x00000030,
887 	0x020e05b4, 0x00000030,
888 	0x020e0528, 0x00000030,
889 	0x020e0520, 0x00000030,
890 	0x020e0514, 0x00000030,
891 	0x020e0510, 0x00000030,
892 	0x020e05bc, 0x00000030,
893 	0x020e05c4, 0x00000030,
894 	0x021b0800, 0xa1390003,
895 	0x021b080c, 0x001b001e,
896 	0x021b0810, 0x002e0029,
897 	0x021b480c, 0x001b002a,
898 	0x021b4810, 0x0019002c,
899 	0x021b083c, 0x43240334,
900 	0x021b0840, 0x0324031a,
901 	0x021b483c, 0x43340344,
902 	0x021b4840, 0x03280276,
903 	0x021b0848, 0x44383A3E,
904 	0x021b4848, 0x3C3C3846,
905 	0x021b0850, 0x2e303230,
906 	0x021b4850, 0x38283E34,
907 	0x021b081c, 0x33333333,
908 	0x021b0820, 0x33333333,
909 	0x021b0824, 0x33333333,
910 	0x021b0828, 0x33333333,
911 	0x021b481c, 0x33333333,
912 	0x021b4820, 0x33333333,
913 	0x021b4824, 0x33333333,
914 	0x021b4828, 0x33333333,
915 	0x021b08c0, 0x24912492,
916 	0x021b48c0, 0x24912492,
917 	0x021b08b8, 0x00000800,
918 	0x021b48b8, 0x00000800,
919 	0x021b0004, 0x00020036,
920 	0x021b0008, 0x09444040,
921 	0x021b000c, 0x898E7955,
922 	0x021b0010, 0xFF328F64,
923 	0x021b0014, 0x01FF00DB,
924 	0x021b0018, 0x00001740,
925 	0x021b001c, 0x00008000,
926 	0x021b002c, 0x000026d2,
927 	0x021b0030, 0x008E1023,
928 	0x021b0040, 0x00000047,
929 	0x021b0400, 0x14420000,
930 	0x021b0000, 0x841A0000,
931 	0x00bb0008, 0x00000004,
932 	0x00bb000c, 0x2891E41A,
933 	0x00bb0038, 0x00000564,
934 	0x00bb0014, 0x00000040,
935 	0x00bb0028, 0x00000020,
936 	0x00bb002c, 0x00000020,
937 	0x021b001c, 0x04088032,
938 	0x021b001c, 0x00008033,
939 	0x021b001c, 0x00048031,
940 	0x021b001c, 0x09408030,
941 	0x021b001c, 0x04008040,
942 	0x021b0020, 0x00005800,
943 	0x021b0818, 0x00011117,
944 	0x021b4818, 0x00011117,
945 	0x021b0004, 0x00025576,
946 	0x021b0404, 0x00011006,
947 	0x021b001c, 0x00000000,
948 	0x020c4068, 0x00C03F3F,
949 	0x020c406c, 0x0030FC03,
950 	0x020c4070, 0x0FFFC000,
951 	0x020c4074, 0x3FF00000,
952 	0x020c4078, 0xFFFFF300,
953 	0x020c407c, 0x0F0000F3,
954 	0x020c4080, 0x00000FFF,
955 	0x020e0010, 0xF00000CF,
956 	0x020e0018, 0x77177717,
957 	0x020e001c, 0x77177717,
958 };
959 
960 static int mx6dl_dcd_table[] = {
961 	0x020e0774, 0x000C0000,
962 	0x020e0754, 0x00000000,
963 	0x020e04ac, 0x00000030,
964 	0x020e04b0, 0x00000030,
965 	0x020e0464, 0x00000030,
966 	0x020e0490, 0x00000030,
967 	0x020e074c, 0x00000030,
968 	0x020e0494, 0x00000030,
969 	0x020e04a0, 0x00000000,
970 	0x020e04b4, 0x00000030,
971 	0x020e04b8, 0x00000030,
972 	0x020e076c, 0x00000030,
973 	0x020e0750, 0x00020000,
974 	0x020e04bc, 0x00000028,
975 	0x020e04c0, 0x00000028,
976 	0x020e04c4, 0x00000028,
977 	0x020e04c8, 0x00000028,
978 	0x020e04cc, 0x00000028,
979 	0x020e04d0, 0x00000028,
980 	0x020e04d4, 0x00000028,
981 	0x020e04d8, 0x00000028,
982 	0x020e0760, 0x00020000,
983 	0x020e0764, 0x00000028,
984 	0x020e0770, 0x00000028,
985 	0x020e0778, 0x00000028,
986 	0x020e077c, 0x00000028,
987 	0x020e0780, 0x00000028,
988 	0x020e0784, 0x00000028,
989 	0x020e078c, 0x00000028,
990 	0x020e0748, 0x00000028,
991 	0x020e0470, 0x00000028,
992 	0x020e0474, 0x00000028,
993 	0x020e0478, 0x00000028,
994 	0x020e047c, 0x00000028,
995 	0x020e0480, 0x00000028,
996 	0x020e0484, 0x00000028,
997 	0x020e0488, 0x00000028,
998 	0x020e048c, 0x00000028,
999 	0x021b0800, 0xa1390003,
1000 	0x021b080c, 0x001F001F,
1001 	0x021b0810, 0x001F001F,
1002 	0x021b480c, 0x001F001F,
1003 	0x021b4810, 0x001F001F,
1004 	0x021b083c, 0x42190217,
1005 	0x021b0840, 0x017B017B,
1006 	0x021b483c, 0x4176017B,
1007 	0x021b4840, 0x015F016C,
1008 	0x021b0848, 0x4C4C4D4C,
1009 	0x021b4848, 0x4A4D4C48,
1010 	0x021b0850, 0x3F3F3F40,
1011 	0x021b4850, 0x3538382E,
1012 	0x021b081c, 0x33333333,
1013 	0x021b0820, 0x33333333,
1014 	0x021b0824, 0x33333333,
1015 	0x021b0828, 0x33333333,
1016 	0x021b481c, 0x33333333,
1017 	0x021b4820, 0x33333333,
1018 	0x021b4824, 0x33333333,
1019 	0x021b4828, 0x33333333,
1020 	0x021b08b8, 0x00000800,
1021 	0x021b48b8, 0x00000800,
1022 	0x021b0004, 0x00020025,
1023 	0x021b0008, 0x00333030,
1024 	0x021b000c, 0x676B5313,
1025 	0x021b0010, 0xB66E8B63,
1026 	0x021b0014, 0x01FF00DB,
1027 	0x021b0018, 0x00001740,
1028 	0x021b001c, 0x00008000,
1029 	0x021b002c, 0x000026d2,
1030 	0x021b0030, 0x006B1023,
1031 	0x021b0040, 0x00000047,
1032 	0x021b0000, 0x841A0000,
1033 	0x021b001c, 0x04008032,
1034 	0x021b001c, 0x00008033,
1035 	0x021b001c, 0x00048031,
1036 	0x021b001c, 0x05208030,
1037 	0x021b001c, 0x04008040,
1038 	0x021b0020, 0x00005800,
1039 	0x021b0818, 0x00011117,
1040 	0x021b4818, 0x00011117,
1041 	0x021b0004, 0x00025565,
1042 	0x021b0404, 0x00011006,
1043 	0x021b001c, 0x00000000,
1044 	0x020c4068, 0x00C03F3F,
1045 	0x020c406c, 0x0030FC03,
1046 	0x020c4070, 0x0FFFC000,
1047 	0x020c4074, 0x3FF00000,
1048 	0x020c4078, 0xFFFFF300,
1049 	0x020c407c, 0x0F0000C3,
1050 	0x020c4080, 0x00000FFF,
1051 	0x020e0010, 0xF00000CF,
1052 	0x020e0018, 0x007F007F,
1053 	0x020e001c, 0x007F007F,
1054 };
1055 
1056 static void ddr_init(int *table, int size)
1057 {
1058 	int i;
1059 
1060 	for (i = 0; i < size / 2 ; i++)
1061 		writel(table[2 * i + 1], table[2 * i]);
1062 }
1063 
1064 static void spl_dram_init(void)
1065 {
1066 	if (is_mx6dq())
1067 		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1068 	else if (is_mx6dqp())
1069 		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
1070 	else if (is_mx6sdl())
1071 		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1072 }
1073 
1074 void board_init_f(ulong dummy)
1075 {
1076 	/* DDR initialization */
1077 	spl_dram_init();
1078 
1079 	/* setup AIPS and disable watchdog */
1080 	arch_cpu_init();
1081 
1082 	ccgr_init();
1083 	gpr_init();
1084 
1085 	/* iomux and setup of i2c */
1086 	board_early_init_f();
1087 
1088 	/* setup GP timer */
1089 	timer_init();
1090 
1091 	/* UART clocks enabled and gd valid - init serial console */
1092 	preloader_console_init();
1093 
1094 	/* Clear the BSS. */
1095 	memset(__bss_start, 0, __bss_end - __bss_start);
1096 
1097 	/* load/boot image from boot device */
1098 	board_init_r(NULL, 0);
1099 }
1100 #endif
1101