1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx6-pins.h>
11 #include <asm/arch/clock.h>
12 #include <asm/errno.h>
13 #include <asm/gpio.h>
14 #include <asm/imx-common/iomux-v3.h>
15 #include <mmc.h>
16 #include <fsl_esdhc.h>
17 #include <miiphy.h>
18 #include <netdev.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
23 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
24 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
25 
26 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
27 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
28 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
29 
30 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
31 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
32 
33 int dram_init(void)
34 {
35 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
36 
37 	return 0;
38 }
39 
40 iomux_v3_cfg_t const uart4_pads[] = {
41 	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
42 	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
43 };
44 
45 iomux_v3_cfg_t const usdhc3_pads[] = {
46 	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
47 	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
48 	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
49 	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
50 	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
51 	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
52 	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
53 	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
54 	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 	MX6_PAD_NANDF_CS0__GPIO6_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
57 };
58 
59 iomux_v3_cfg_t const usdhc4_pads[] = {
60 	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
65 	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 };
71 
72 iomux_v3_cfg_t const enet_pads[] = {
73 	MX6_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 	MX6_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 	MX6_PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 	MX6_PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 	MX6_PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 	MX6_PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 	MX6_PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 	MX6_PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 	MX6_PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 	MX6_PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 	MX6_PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 	MX6_PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 };
89 
90 
91 static void setup_iomux_uart(void)
92 {
93 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
94 }
95 
96 static void setup_iomux_enet(void)
97 {
98 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
99 }
100 
101 #ifdef CONFIG_FSL_ESDHC
102 struct fsl_esdhc_cfg usdhc_cfg[2] = {
103 	{USDHC3_BASE_ADDR},
104 	{USDHC4_BASE_ADDR},
105 };
106 
107 int board_mmc_getcd(struct mmc *mmc)
108 {
109 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
110 	int ret;
111 
112 	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
113 		gpio_direction_input(IMX_GPIO_NR(6, 11));
114 		ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
115 	} else /* Don't have the CD GPIO pin on board */
116 		ret = 1;
117 
118 	return ret;
119 }
120 
121 int board_mmc_init(bd_t *bis)
122 {
123 	s32 status = 0;
124 	u32 index = 0;
125 
126 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
127 	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
128 
129 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
130 		switch (index) {
131 		case 0:
132 			imx_iomux_v3_setup_multiple_pads(
133 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
134 			break;
135 		case 1:
136 			imx_iomux_v3_setup_multiple_pads(
137 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
138 			break;
139 		default:
140 			printf("Warning: you configured more USDHC controllers"
141 				"(%d) then supported by the board (%d)\n",
142 				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
143 			return status;
144 		}
145 
146 		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
147 	}
148 
149 	return status;
150 }
151 #endif
152 
153 #define MII_MMD_ACCESS_CTRL_REG		0xd
154 #define MII_MMD_ACCESS_ADDR_DATA_REG	0xe
155 #define MII_DBG_PORT_REG		0x1d
156 #define MII_DBG_PORT2_REG		0x1e
157 
158 int fecmxc_mii_postcall(int phy)
159 {
160 	unsigned short val;
161 
162 	/*
163 	 * Due to the i.MX6Q Armadillo2 board HW design,there is
164 	 * no 125Mhz clock input from SOC. In order to use RGMII,
165 	 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
166 	 */
167 	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
168 	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
169 	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
170 	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
171 	val &= 0xffe3;
172 	val |= 0x18;
173 	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
174 
175 	/* For the RGMII phy, we need enable tx clock delay */
176 	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
177 	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
178 	val |= 0x0100;
179 	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
180 
181 	miiphy_write("FEC", phy, MII_BMCR, 0xa100);
182 
183 	return 0;
184 }
185 
186 int board_eth_init(bd_t *bis)
187 {
188 	struct eth_device *dev;
189 	int ret;
190 
191 	ret = cpu_eth_init(bis);
192 	if (ret) {
193 		printf("FEC MXC: %s:failed\n", __func__);
194 		return ret;
195 	}
196 
197 	dev = eth_get_dev_by_name("FEC");
198 	if (!dev) {
199 		printf("FEC MXC: Unable to get FEC device entry\n");
200 		return -EINVAL;
201 	}
202 
203 	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
204 	if (ret) {
205 		printf("FEC MXC: Unable to register FEC mii postcall\n");
206 		return ret;
207 	}
208 
209 	return 0;
210 }
211 
212 int board_early_init_f(void)
213 {
214 	setup_iomux_uart();
215 	setup_iomux_enet();
216 
217 	return 0;
218 }
219 
220 int board_init(void)
221 {
222 	/* address of boot parameters */
223 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
224 
225 	return 0;
226 }
227 
228 int checkboard(void)
229 {
230 	puts("Board: MX6Q-Armadillo2\n");
231 
232 	return 0;
233 }
234