1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/mx6-pins.h> 10 #include <asm/arch/clock.h> 11 #include <linux/errno.h> 12 #include <asm/gpio.h> 13 #include <asm/mach-imx/iomux-v3.h> 14 #include <mmc.h> 15 #include <fsl_esdhc.h> 16 #include <miiphy.h> 17 #include <netdev.h> 18 #include <usb.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 23 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 24 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 25 26 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 27 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 28 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 30 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 31 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 32 33 int dram_init(void) 34 { 35 #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ 36 defined(CONFIG_DDR_32BIT) 37 gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2; 38 #else 39 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; 40 #endif 41 42 return 0; 43 } 44 45 iomux_v3_cfg_t const uart4_pads[] = { 46 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 47 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 48 }; 49 50 iomux_v3_cfg_t const usdhc3_pads[] = { 51 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 52 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 53 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 54 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 55 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 56 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 57 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 58 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 59 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 62 }; 63 64 iomux_v3_cfg_t const usdhc4_pads[] = { 65 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 }; 76 77 iomux_v3_cfg_t const enet_pads[] = { 78 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 87 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 88 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 89 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 90 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 91 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 92 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 93 }; 94 95 96 static void setup_iomux_uart(void) 97 { 98 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 99 } 100 101 static void setup_iomux_enet(void) 102 { 103 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 104 } 105 106 #ifdef CONFIG_FSL_ESDHC 107 struct fsl_esdhc_cfg usdhc_cfg[2] = { 108 {USDHC3_BASE_ADDR}, 109 {USDHC4_BASE_ADDR}, 110 }; 111 112 int board_mmc_get_env_dev(int devno) 113 { 114 return devno - 2; 115 } 116 117 int board_mmc_getcd(struct mmc *mmc) 118 { 119 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 120 int ret; 121 122 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 123 gpio_direction_input(IMX_GPIO_NR(6, 11)); 124 ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); 125 } else /* Don't have the CD GPIO pin on board */ 126 ret = 1; 127 128 return ret; 129 } 130 131 int board_mmc_init(bd_t *bis) 132 { 133 int ret; 134 u32 index = 0; 135 136 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 137 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 138 139 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 140 switch (index) { 141 case 0: 142 imx_iomux_v3_setup_multiple_pads( 143 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 144 break; 145 case 1: 146 imx_iomux_v3_setup_multiple_pads( 147 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 148 break; 149 default: 150 printf("Warning: you configured more USDHC controllers" 151 "(%d) then supported by the board (%d)\n", 152 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 153 return -EINVAL; 154 } 155 156 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 157 if (ret) 158 return ret; 159 } 160 161 return 0; 162 } 163 #endif 164 165 #define MII_MMD_ACCESS_CTRL_REG 0xd 166 #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe 167 #define MII_DBG_PORT_REG 0x1d 168 #define MII_DBG_PORT2_REG 0x1e 169 170 int fecmxc_mii_postcall(int phy) 171 { 172 unsigned short val; 173 174 /* 175 * Due to the i.MX6Q Armadillo2 board HW design,there is 176 * no 125Mhz clock input from SOC. In order to use RGMII, 177 * We need enable AR8031 ouput a 125MHz clk from CLK_25M 178 */ 179 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); 180 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); 181 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); 182 miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); 183 val &= 0xffe3; 184 val |= 0x18; 185 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); 186 187 /* For the RGMII phy, we need enable tx clock delay */ 188 miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); 189 miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); 190 val |= 0x0100; 191 miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); 192 193 miiphy_write("FEC", phy, MII_BMCR, 0xa100); 194 195 return 0; 196 } 197 198 int board_eth_init(bd_t *bis) 199 { 200 struct eth_device *dev; 201 int ret = cpu_eth_init(bis); 202 203 if (ret) 204 return ret; 205 206 dev = eth_get_dev_by_name("FEC"); 207 if (!dev) { 208 printf("FEC MXC: Unable to get FEC device entry\n"); 209 return -EINVAL; 210 } 211 212 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); 213 if (ret) { 214 printf("FEC MXC: Unable to register FEC mii postcall\n"); 215 return ret; 216 } 217 218 return 0; 219 } 220 221 #ifdef CONFIG_USB_EHCI_MX6 222 #define USB_OTHERREGS_OFFSET 0x800 223 #define UCTRL_PWR_POL (1 << 9) 224 225 static iomux_v3_cfg_t const usb_otg_pads[] = { 226 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 227 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 228 }; 229 230 static void setup_usb(void) 231 { 232 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 233 ARRAY_SIZE(usb_otg_pads)); 234 235 /* 236 * set daisy chain for otg_pin_id on 6q. 237 * for 6dl, this bit is reserved 238 */ 239 imx_iomux_set_gpr_register(1, 13, 1, 1); 240 } 241 242 int board_ehci_hcd_init(int port) 243 { 244 u32 *usbnc_usb_ctrl; 245 246 if (port > 0) 247 return -EINVAL; 248 249 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 250 port * 4); 251 252 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 253 254 return 0; 255 } 256 #endif 257 258 int board_early_init_f(void) 259 { 260 setup_iomux_uart(); 261 setup_iomux_enet(); 262 263 return 0; 264 } 265 266 int board_init(void) 267 { 268 /* address of boot parameters */ 269 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 270 271 #ifdef CONFIG_USB_EHCI_MX6 272 setup_usb(); 273 #endif 274 275 return 0; 276 } 277 278 int checkboard(void) 279 { 280 #ifdef CONFIG_MX6DL 281 puts("Board: MX6DL-Armadillo2\n"); 282 #else 283 puts("Board: MX6Q-Armadillo2\n"); 284 #endif 285 286 return 0; 287 } 288