1 /* 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/mx6x_pins.h> 27 #include <asm/arch/iomux-v3.h> 28 #include <asm/errno.h> 29 #include <asm/gpio.h> 30 #include <mmc.h> 31 #include <fsl_esdhc.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 40 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 int dram_init(void) 44 { 45 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 46 47 return 0; 48 } 49 50 iomux_v3_cfg_t uart4_pads[] = { 51 MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 52 MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 53 }; 54 55 iomux_v3_cfg_t usdhc3_pads[] = { 56 MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 57 MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 58 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 59 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 62 MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 63 MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 64 MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65 MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 67 }; 68 69 iomux_v3_cfg_t usdhc4_pads[] = { 70 MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 }; 81 82 static void setup_iomux_uart(void) 83 { 84 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 85 } 86 87 #ifdef CONFIG_FSL_ESDHC 88 struct fsl_esdhc_cfg usdhc_cfg[2] = { 89 {USDHC3_BASE_ADDR, 1}, 90 {USDHC4_BASE_ADDR, 1}, 91 }; 92 93 int board_mmc_getcd(u8 *cd, struct mmc *mmc) 94 { 95 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 96 97 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 98 gpio_direction_input(171); /*GPIO6_11*/ 99 *cd = gpio_get_value(171); 100 } else /* Don't have the CD GPIO pin on board */ 101 *cd = 0; 102 103 return 0; 104 } 105 106 int board_mmc_init(bd_t *bis) 107 { 108 s32 status = 0; 109 u32 index = 0; 110 111 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 112 switch (index) { 113 case 0: 114 imx_iomux_v3_setup_multiple_pads( 115 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 116 break; 117 case 1: 118 imx_iomux_v3_setup_multiple_pads( 119 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 120 break; 121 default: 122 printf("Warning: you configured more USDHC controllers" 123 "(%d) then supported by the board (%d)\n", 124 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 125 return status; 126 } 127 128 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 129 } 130 131 return status; 132 } 133 #endif 134 135 int board_early_init_f(void) 136 { 137 setup_iomux_uart(); 138 139 return 0; 140 } 141 142 int board_init(void) 143 { 144 /* address of boot parameters */ 145 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 146 147 return 0; 148 } 149 150 int checkboard(void) 151 { 152 puts("Board: MX6Q-Armadillo2\n"); 153 154 return 0; 155 } 156