1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx6x_pins.h>
27 #include <asm/errno.h>
28 #include <asm/gpio.h>
29 #include <asm/imx-common/iomux-v3.h>
30 #include <mmc.h>
31 #include <fsl_esdhc.h>
32 #include <miiphy.h>
33 #include <netdev.h>
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
38 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
39 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
40 
41 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
42 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
43 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
44 
45 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
46 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
47 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
48 
49 int dram_init(void)
50 {
51 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
52 
53 	return 0;
54 }
55 
56 iomux_v3_cfg_t uart4_pads[] = {
57 	MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
58 	MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
59 };
60 
61 iomux_v3_cfg_t usdhc3_pads[] = {
62 	MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 	MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
65 	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 	MX6Q_PAD_NANDF_CS0__GPIO_6_11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
73 };
74 
75 iomux_v3_cfg_t usdhc4_pads[] = {
76 	MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 	MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 	MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 	MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 	MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 };
87 
88 iomux_v3_cfg_t enet_pads[] = {
89 	MX6Q_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 	MX6Q_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 };
105 
106 
107 static void setup_iomux_uart(void)
108 {
109 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
110 }
111 
112 static void setup_iomux_enet(void)
113 {
114 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
115 }
116 
117 #ifdef CONFIG_FSL_ESDHC
118 struct fsl_esdhc_cfg usdhc_cfg[2] = {
119 	{USDHC3_BASE_ADDR, 1},
120 	{USDHC4_BASE_ADDR, 1},
121 };
122 
123 int board_mmc_getcd(struct mmc *mmc)
124 {
125 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
126 	int ret;
127 
128 	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
129 		gpio_direction_input(171); /*GPIO6_11*/
130 		ret = !gpio_get_value(171);
131 	} else /* Don't have the CD GPIO pin on board */
132 		ret = 1;
133 
134 	return ret;
135 }
136 
137 int board_mmc_init(bd_t *bis)
138 {
139 	s32 status = 0;
140 	u32 index = 0;
141 
142 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
143 		switch (index) {
144 		case 0:
145 			imx_iomux_v3_setup_multiple_pads(
146 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
147 			break;
148 		case 1:
149 			imx_iomux_v3_setup_multiple_pads(
150 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
151 			break;
152 		default:
153 			printf("Warning: you configured more USDHC controllers"
154 				"(%d) then supported by the board (%d)\n",
155 				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
156 			return status;
157 		}
158 
159 		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
160 	}
161 
162 	return status;
163 }
164 #endif
165 
166 #define MII_MMD_ACCESS_CTRL_REG		0xd
167 #define MII_MMD_ACCESS_ADDR_DATA_REG	0xe
168 #define MII_DBG_PORT_REG		0x1d
169 #define MII_DBG_PORT2_REG		0x1e
170 
171 int fecmxc_mii_postcall(int phy)
172 {
173 	unsigned short val;
174 
175 	/*
176 	 * Due to the i.MX6Q Armadillo2 board HW design,there is
177 	 * no 125Mhz clock input from SOC. In order to use RGMII,
178 	 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
179 	 */
180 	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
181 	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
182 	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
183 	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
184 	val &= 0xffe3;
185 	val |= 0x18;
186 	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
187 
188 	/* For the RGMII phy, we need enable tx clock delay */
189 	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
190 	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
191 	val |= 0x0100;
192 	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
193 
194 	miiphy_write("FEC", phy, MII_BMCR, 0xa100);
195 
196 	return 0;
197 }
198 
199 int board_eth_init(bd_t *bis)
200 {
201 	struct eth_device *dev;
202 	int ret;
203 
204 	ret = cpu_eth_init(bis);
205 	if (ret) {
206 		printf("FEC MXC: %s:failed\n", __func__);
207 		return ret;
208 	}
209 
210 	dev = eth_get_dev_by_name("FEC");
211 	if (!dev) {
212 		printf("FEC MXC: Unable to get FEC device entry\n");
213 		return -EINVAL;
214 	}
215 
216 	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
217 	if (ret) {
218 		printf("FEC MXC: Unable to register FEC mii postcall\n");
219 		return ret;
220 	}
221 
222 	return 0;
223 }
224 
225 int board_early_init_f(void)
226 {
227 	setup_iomux_uart();
228 	setup_iomux_enet();
229 
230 	return 0;
231 }
232 
233 int board_init(void)
234 {
235 	/* address of boot parameters */
236 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
237 
238 	return 0;
239 }
240 
241 int checkboard(void)
242 {
243 	puts("Board: MX6Q-Armadillo2\n");
244 
245 	return 0;
246 }
247