1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 * Jason Liu <r64343@freescale.com> 5 * 6 * Refer doc/README.imximage for more details about how-to configure 7 * and create imximage boot image 8 * 9 * The syntax is taken as close as possible with the kwbimage 10 */ 11 12/* image version */ 13IMAGE_VERSION 2 14 15/* 16 * Boot Device : one of 17 * spi, sd (the board has no nand neither onenand) 18 */ 19BOOT_FROM sd 20 21/* 22 * Device Configuration Data (DCD) 23 * 24 * Each entry must have the format: 25 * Addr-type Address Value 26 * 27 * where: 28 * Addr-type register length (1,2 or 4 bytes) 29 * Address absolute address of the register 30 * value value to be stored in the register 31 */ 32 33 34 35#ifdef CONFIG_MX6DL_LPDDR2 36 37/* IOMUX SETTINGS */ 38/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ 39DATA 4 0x020E04bc 0x00003028 40/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ 41DATA 4 0x020E04c0 0x00003028 42/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ 43DATA 4 0x020E04c4 0x00003028 44/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ 45DATA 4 0x020E04c8 0x00003028 46/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ 47DATA 4 0x020E04cc 0x00003028 48/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ 49DATA 4 0x020E04d0 0x00003028 50/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ 51DATA 4 0x020E04d4 0x00003028 52/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ 53DATA 4 0x020E04d8 0x00003028 54 55/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ 56DATA 4 0x020E0470 0x00000038 57/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ 58DATA 4 0x020E0474 0x00000038 59/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ 60DATA 4 0x020E0478 0x00000038 61/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ 62DATA 4 0x020E047c 0x00000038 63/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ 64DATA 4 0x020E0480 0x00000038 65/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ 66DATA 4 0x020E0484 0x00000038 67/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ 68DATA 4 0x020E0488 0x00000038 69/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ 70DATA 4 0x020E048c 0x00000038 71/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ 72DATA 4 0x020E0464 0x00000038 73/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ 74DATA 4 0x020E0490 0x00000038 75/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ 76DATA 4 0x020E04ac 0x00000038 77/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ 78DATA 4 0x020E04b0 0x00000038 79/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ 80DATA 4 0x020E0494 0x00000038 81/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ 82DATA 4 0x020E04a4 0x00000038 83/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ 84DATA 4 0x020E04a8 0x00000038 85/* 86 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 87 * DSE can be configured using Group Control Register: 88 * IOMUXC_SW_PAD_CTL_GRP_CTLDS 89 */ 90DATA 4 0x020E04a0 0x00000000 91/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ 92DATA 4 0x020E04b4 0x00000038 93/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ 94DATA 4 0x020E04b8 0x00000038 95/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ 96DATA 4 0x020E0764 0x00000038 97/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ 98DATA 4 0x020E0770 0x00000038 99/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ 100DATA 4 0x020E0778 0x00000038 101/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ 102DATA 4 0x020E077c 0x00000038 103/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ 104DATA 4 0x020E0780 0x00000038 105/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ 106DATA 4 0x020E0784 0x00000038 107/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ 108DATA 4 0x020E078c 0x00000038 109/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ 110DATA 4 0x020E0748 0x00000038 111/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ 112DATA 4 0x020E074c 0x00000038 113/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ 114DATA 4 0x020E076c 0x00000038 115/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ 116DATA 4 0x020E0750 0x00020000 117/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ 118DATA 4 0x020E0754 0x00000000 119/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ 120DATA 4 0x020E0760 0x00020000 121/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ 122DATA 4 0x020E0774 0x00080000 123 124/* 125 * DDR Controller Registers 126 * 127 * Manufacturer: Mocron 128 * Device Part Number: MT42L64M64D2KH-18 129 * Clock Freq.: 528MHz 130 * MMDC channels: Both MMDC0, MMDC1 131 *Density per CS in Gb: 256M 132 * Chip Selects used: 2 133 * Number of Banks: 8 134 * Row address: 14 135 * Column address: 9 136 * Data bus width 32 137 */ 138 139/* MMDC_P0_BASE_ADDR = 0x021b0000 */ 140/* MMDC_P1_BASE_ADDR = 0x021b4000 */ 141 142/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ 143DATA 4 0x021b001c 0x00008000 144 145/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ 146DATA 4 0x021b401c 0x00008000 147 148/*LPDDR2 ZQ params */ 149DATA 4 0x021b085c 0x1b5f01ff 150DATA 4 0x021b485c 0x1b5f01ff 151 152/* Calibration setup. */ 153/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ 154DATA 4 0x021b0800 0xa1390003 155 156/*ca bus abs delay */ 157DATA 4 0x021b0890 0x00400000 158/*ca bus abs delay */ 159DATA 4 0x021b4890 0x00400000 160/* values of 20,40,50,60,7f tried. no difference seen */ 161 162/* DDR_PHY_P1_MPWRCADL */ 163DATA 4 0x021b48bc 0x00055555 164 165/*frc_msr.*/ 166DATA 4 0x021b08b8 0x00000800 167/*frc_msr.*/ 168DATA 4 0x021b48b8 0x00000800 169 170/* DDR_PHY_P0_MPREDQBY0DL3 */ 171DATA 4 0x021b081c 0x33333333 172/* DDR_PHY_P0_MPREDQBY1DL3 */ 173DATA 4 0x021b0820 0x33333333 174/* DDR_PHY_P0_MPREDQBY2DL3 */ 175DATA 4 0x021b0824 0x33333333 176/* DDR_PHY_P0_MPREDQBY3DL3 */ 177DATA 4 0x021b0828 0x33333333 178/* DDR_PHY_P1_MPREDQBY0DL3 */ 179DATA 4 0x021b481c 0x33333333 180/* DDR_PHY_P1_MPREDQBY1DL3 */ 181DATA 4 0x021b4820 0x33333333 182/* DDR_PHY_P1_MPREDQBY2DL3 */ 183DATA 4 0x021b4824 0x33333333 184/* DDR_PHY_P1_MPREDQBY3DL3 */ 185DATA 4 0x021b4828 0x33333333 186 187/* 188 * Read and write data delay, per byte. 189 * For optimized DDR operation it is recommended to run mmdc_calibration 190 * on your board, and replace 4 delay register assigns with resulted values 191 * Note: 192 * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section 193 * should be skipped, or the write/read calibration comming after that 194 * will stall 195 * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. 196 */ 197 198DATA 4 0x021b0848 0x4b4b524f 199DATA 4 0x021b4848 0x494f4c44 200 201DATA 4 0x021b0850 0x3c3d303c 202DATA 4 0x021b4850 0x3c343d38 203 204/*dqs gating dis */ 205DATA 4 0x021b083c 0x20000000 206DATA 4 0x021b0840 0x0 207DATA 4 0x021b483c 0x20000000 208DATA 4 0x021b4840 0x0 209 210/*clk delay */ 211DATA 4 0x021b0858 0xa00 212/*clk delay */ 213DATA 4 0x021b4858 0xa00 214 215/*frc_msr */ 216DATA 4 0x021b08b8 0x00000800 217/*frc_msr */ 218DATA 4 0x021b48b8 0x00000800 219/* Calibration setup end */ 220 221/* Channel0 - startng address 0x80000000 */ 222/* MMDC0_MDCFG0 */ 223DATA 4 0x021b000c 0x34386145 224 225/* MMDC0_MDPDC */ 226DATA 4 0x021b0004 0x00020036 227/* MMDC0_MDCFG1 */ 228DATA 4 0x021b0010 0x00100c83 229/* MMDC0_MDCFG2 */ 230DATA 4 0x021b0014 0x000000Dc 231/* MMDC0_MDMISC */ 232DATA 4 0x021b0018 0x0000174C 233/* MMDC0_MDRWD;*/ 234DATA 4 0x021b002c 0x0f9f26d2 235/* MMDC0_MDOR */ 236DATA 4 0x021b0030 0x009f0e10 237/* MMDC0_MDCFG3LP */ 238DATA 4 0x021b0038 0x00190778 239/* MMDC0_MDOTC */ 240DATA 4 0x021b0008 0x00000000 241 242/* CS0_END */ 243DATA 4 0x021b0040 0x0000005f 244/* ROC */ 245DATA 4 0x021b0404 0x0000000f 246 247/* MMDC0_MDCTL */ 248DATA 4 0x021b0000 0xc3010000 249 250/* Channel1 - starting address 0x10000000 */ 251/* MMDC1_MDCFG0 */ 252DATA 4 0x021b400c 0x34386145 253 254/* MMDC1_MDPDC */ 255DATA 4 0x021b4004 0x00020036 256/* MMDC1_MDCFG1 */ 257DATA 4 0x021b4010 0x00100c83 258/* MMDC1_MDCFG2 */ 259DATA 4 0x021b4014 0x000000Dc 260/* MMDC1_MDMISC */ 261DATA 4 0x021b4018 0x0000174C 262/* MMDC1_MDRWD;*/ 263DATA 4 0x021b402c 0x0f9f26d2 264/* MMDC1_MDOR */ 265DATA 4 0x021b4030 0x009f0e10 266/* MMDC1_MDCFG3LP */ 267DATA 4 0x021b4038 0x00190778 268/* MMDC1_MDOTC */ 269DATA 4 0x021b4008 0x00000000 270 271/* CS0_END */ 272DATA 4 0x021b4040 0x0000003f 273 274/* MMDC1_MDCTL */ 275DATA 4 0x021b4000 0xc3010000 276 277/* Channel0 : Configure DDR device:*/ 278/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ 279DATA 4 0x021b001c 0x003f8030 280/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ 281DATA 4 0x021b001c 0xff0a8030 282/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ 283DATA 4 0x021b001c 0xa2018030 284/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ 285DATA 4 0x021b001c 0x06028030 286/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ 287DATA 4 0x021b001c 0x01038030 288 289/* Channel1 : Configure DDR device:*/ 290/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ 291DATA 4 0x021b401c 0x003f8030 292/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ 293DATA 4 0x021b401c 0xff0a8030 294/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ 295DATA 4 0x021b401c 0xa2018030 296/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ 297DATA 4 0x021b401c 0x06028030 298/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ 299DATA 4 0x021b401c 0x01038030 300 301/* MMDC0_MDREF */ 302DATA 4 0x021b0020 0x00005800 303/* MMDC1_MDREF */ 304DATA 4 0x021b4020 0x00005800 305 306/* DDR_PHY_P0_MPODTCTRL */ 307DATA 4 0x021b0818 0x0 308/* DDR_PHY_P1_MPODTCTRL */ 309DATA 4 0x021b4818 0x0 310 311/* 312 * calibration values based on calibration compare of 0x00ffff00: 313 * Note, these calibration values are based on Freescale's board 314 * May need to run calibration on target board to fine tune these 315 */ 316 317/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ 318DATA 4 0x021b0800 0xa1310003 319 320/* DDR_PHY_P0_MPMUR0, frc_msr */ 321DATA 4 0x021b08b8 0x00000800 322/* DDR_PHY_P1_MPMUR0, frc_msr */ 323DATA 4 0x021b48b8 0x00000800 324 325/* 326 * MMDC0_MDSCR, clear this register 327 * (especially the configuration bit as initialization is complete) 328 */ 329DATA 4 0x021b001c 0x00000000 330/* 331 * MMDC0_MDSCR, clear this register 332 * (especially the configuration bit as initialization is complete) 333 */ 334DATA 4 0x021b401c 0x00000000 335 336DATA 4 0x020c4068 0x00C03F3F 337DATA 4 0x020c406c 0x0030FC03 338DATA 4 0x020c4070 0x0FFFC000 339DATA 4 0x020c4074 0x3FF00000 340DATA 4 0x020c4078 0x00FFF300 341DATA 4 0x020c407c 0x0F0000C3 342DATA 4 0x020c4080 0x000003FF 343 344DATA 4 0x020e0010 0xF00000CF 345DATA 4 0x020e0018 0x007F007F 346DATA 4 0x020e001c 0x007F007F 347 348#else /* CONFIG_MX6DL_LPDDR2 */ 349 350DATA 4 0x020e0798 0x000c0000 351DATA 4 0x020e0758 0x00000000 352DATA 4 0x020e0588 0x00000030 353DATA 4 0x020e0594 0x00000030 354DATA 4 0x020e056c 0x00000030 355DATA 4 0x020e0578 0x00000030 356DATA 4 0x020e074c 0x00000030 357DATA 4 0x020e057c 0x00000030 358DATA 4 0x020e0590 0x00003000 359DATA 4 0x020e0598 0x00003000 360DATA 4 0x020e058c 0x00000000 361DATA 4 0x020e059c 0x00003030 362DATA 4 0x020e05a0 0x00003030 363DATA 4 0x020e078c 0x00000030 364DATA 4 0x020e0750 0x00020000 365DATA 4 0x020e05a8 0x00000030 366DATA 4 0x020e05b0 0x00000030 367DATA 4 0x020e0524 0x00000030 368DATA 4 0x020e051c 0x00000030 369DATA 4 0x020e0518 0x00000030 370DATA 4 0x020e050c 0x00000030 371DATA 4 0x020e05b8 0x00000030 372DATA 4 0x020e05c0 0x00000030 373DATA 4 0x020e0774 0x00020000 374DATA 4 0x020e0784 0x00000030 375DATA 4 0x020e0788 0x00000030 376DATA 4 0x020e0794 0x00000030 377DATA 4 0x020e079c 0x00000030 378DATA 4 0x020e07a0 0x00000030 379DATA 4 0x020e07a4 0x00000030 380DATA 4 0x020e07a8 0x00000030 381DATA 4 0x020e0748 0x00000030 382DATA 4 0x020e05ac 0x00000030 383DATA 4 0x020e05b4 0x00000030 384DATA 4 0x020e0528 0x00000030 385DATA 4 0x020e0520 0x00000030 386DATA 4 0x020e0514 0x00000030 387DATA 4 0x020e0510 0x00000030 388DATA 4 0x020e05bc 0x00000030 389DATA 4 0x020e05c4 0x00000030 390 391DATA 4 0x021b0800 0xa1390003 392DATA 4 0x021b4800 0xa1390003 393DATA 4 0x021b080c 0x001F001F 394DATA 4 0x021b0810 0x001F001F 395DATA 4 0x021b480c 0x00370037 396DATA 4 0x021b4810 0x00370037 397DATA 4 0x021b083c 0x422f0220 398DATA 4 0x021b0840 0x021f0219 399DATA 4 0x021b483C 0x422f0220 400DATA 4 0x021b4840 0x022d022f 401DATA 4 0x021b0848 0x47494b49 402DATA 4 0x021b4848 0x48484c47 403DATA 4 0x021b0850 0x39382b2f 404DATA 4 0x021b4850 0x2f35312c 405DATA 4 0x021b081c 0x33333333 406DATA 4 0x021b0820 0x33333333 407DATA 4 0x021b0824 0x33333333 408DATA 4 0x021b0828 0x33333333 409DATA 4 0x021b481c 0x33333333 410DATA 4 0x021b4820 0x33333333 411DATA 4 0x021b4824 0x33333333 412DATA 4 0x021b4828 0x33333333 413DATA 4 0x021b08b8 0x00000800 414DATA 4 0x021b48b8 0x00000800 415DATA 4 0x021b0004 0x0002002d 416DATA 4 0x021b0008 0x00333030 417 418DATA 4 0x021b000c 0x40445323 419DATA 4 0x021b0010 0xb66e8c63 420 421DATA 4 0x021b0014 0x01ff00db 422DATA 4 0x021b0018 0x00081740 423DATA 4 0x021b001c 0x00008000 424DATA 4 0x021b002c 0x000026d2 425DATA 4 0x021b0030 0x00440e21 426#ifdef CONFIG_DDR_32BIT 427DATA 4 0x021b0040 0x00000017 428DATA 4 0x021b0000 0xc3190000 429#else 430DATA 4 0x021b0040 0x00000027 431DATA 4 0x021b0000 0xc31a0000 432#endif 433DATA 4 0x021b001c 0x04008032 434DATA 4 0x021b001c 0x0400803a 435DATA 4 0x021b001c 0x00008033 436DATA 4 0x021b001c 0x0000803b 437DATA 4 0x021b001c 0x00428031 438DATA 4 0x021b001c 0x00428039 439DATA 4 0x021b001c 0x07208030 440DATA 4 0x021b001c 0x07208038 441DATA 4 0x021b001c 0x04008040 442DATA 4 0x021b001c 0x04008048 443DATA 4 0x021b0020 0x00005800 444DATA 4 0x021b0818 0x00000007 445DATA 4 0x021b4818 0x00000007 446DATA 4 0x021b0004 0x0002556d 447DATA 4 0x021b4004 0x00011006 448DATA 4 0x021b001c 0x00000000 449 450DATA 4 0x020c4068 0x00C03F3F 451DATA 4 0x020c406c 0x0030FC03 452DATA 4 0x020c4070 0x0FFFC000 453DATA 4 0x020c4074 0x3FF00000 454DATA 4 0x020c4078 0x00FFF300 455DATA 4 0x020c407c 0x0F0000C3 456DATA 4 0x020c4080 0x000003FF 457 458DATA 4 0x020e0010 0xF00000CF 459DATA 4 0x020e0018 0x007F007F 460DATA 4 0x020e001c 0x007F007F 461#endif /* CONFIG_MX6DL_LPDDR2 */ 462