1/* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Refer doc/README.imximage for more details about how-to configure 8 * and create imximage boot image 9 * 10 * The syntax is taken as close as possible with the kwbimage 11 */ 12 13/* image version */ 14IMAGE_VERSION 2 15 16/* 17 * Boot Device : one of 18 * spi, sd (the board has no nand neither onenand) 19 */ 20BOOT_FROM sd 21 22/* 23 * Device Configuration Data (DCD) 24 * 25 * Each entry must have the format: 26 * Addr-type Address Value 27 * 28 * where: 29 * Addr-type register length (1,2 or 4 bytes) 30 * Address absolute address of the register 31 * value value to be stored in the register 32 */ 33 34 35 36#ifdef CONFIG_MX6DL_LPDDR2 37 38/* IOMUX SETTINGS */ 39/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ 40DATA 4 0x020E04bc 0x00003028 41/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ 42DATA 4 0x020E04c0 0x00003028 43/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ 44DATA 4 0x020E04c4 0x00003028 45/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ 46DATA 4 0x020E04c8 0x00003028 47/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ 48DATA 4 0x020E04cc 0x00003028 49/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ 50DATA 4 0x020E04d0 0x00003028 51/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ 52DATA 4 0x020E04d4 0x00003028 53/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ 54DATA 4 0x020E04d8 0x00003028 55 56/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ 57DATA 4 0x020E0470 0x00000038 58/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ 59DATA 4 0x020E0474 0x00000038 60/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ 61DATA 4 0x020E0478 0x00000038 62/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ 63DATA 4 0x020E047c 0x00000038 64/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ 65DATA 4 0x020E0480 0x00000038 66/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ 67DATA 4 0x020E0484 0x00000038 68/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ 69DATA 4 0x020E0488 0x00000038 70/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ 71DATA 4 0x020E048c 0x00000038 72/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ 73DATA 4 0x020E0464 0x00000038 74/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ 75DATA 4 0x020E0490 0x00000038 76/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ 77DATA 4 0x020E04ac 0x00000038 78/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ 79DATA 4 0x020E04b0 0x00000038 80/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ 81DATA 4 0x020E0494 0x00000038 82/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ 83DATA 4 0x020E04a4 0x00000038 84/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ 85DATA 4 0x020E04a8 0x00000038 86/* 87 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 88 * DSE can be configured using Group Control Register: 89 * IOMUXC_SW_PAD_CTL_GRP_CTLDS 90 */ 91DATA 4 0x020E04a0 0x00000000 92/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ 93DATA 4 0x020E04b4 0x00000038 94/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ 95DATA 4 0x020E04b8 0x00000038 96/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ 97DATA 4 0x020E0764 0x00000038 98/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ 99DATA 4 0x020E0770 0x00000038 100/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ 101DATA 4 0x020E0778 0x00000038 102/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ 103DATA 4 0x020E077c 0x00000038 104/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ 105DATA 4 0x020E0780 0x00000038 106/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ 107DATA 4 0x020E0784 0x00000038 108/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ 109DATA 4 0x020E078c 0x00000038 110/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ 111DATA 4 0x020E0748 0x00000038 112/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ 113DATA 4 0x020E074c 0x00000038 114/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ 115DATA 4 0x020E076c 0x00000038 116/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ 117DATA 4 0x020E0750 0x00020000 118/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ 119DATA 4 0x020E0754 0x00000000 120/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ 121DATA 4 0x020E0760 0x00020000 122/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ 123DATA 4 0x020E0774 0x00080000 124 125/* 126 * DDR Controller Registers 127 * 128 * Manufacturer: Mocron 129 * Device Part Number: MT42L64M64D2KH-18 130 * Clock Freq.: 528MHz 131 * MMDC channels: Both MMDC0, MMDC1 132 *Density per CS in Gb: 256M 133 * Chip Selects used: 2 134 * Number of Banks: 8 135 * Row address: 14 136 * Column address: 9 137 * Data bus width 32 138 */ 139 140/* MMDC_P0_BASE_ADDR = 0x021b0000 */ 141/* MMDC_P1_BASE_ADDR = 0x021b4000 */ 142 143/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ 144DATA 4 0x021b001c 0x00008000 145 146/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ 147DATA 4 0x021b401c 0x00008000 148 149/*LPDDR2 ZQ params */ 150DATA 4 0x021b085c 0x1b5f01ff 151DATA 4 0x021b485c 0x1b5f01ff 152 153/* Calibration setup. */ 154/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ 155DATA 4 0x021b0800 0xa1390003 156 157/*ca bus abs delay */ 158DATA 4 0x021b0890 0x00400000 159/*ca bus abs delay */ 160DATA 4 0x021b4890 0x00400000 161/* values of 20,40,50,60,7f tried. no difference seen */ 162 163/* DDR_PHY_P1_MPWRCADL */ 164DATA 4 0x021b48bc 0x00055555 165 166/*frc_msr.*/ 167DATA 4 0x021b08b8 0x00000800 168/*frc_msr.*/ 169DATA 4 0x021b48b8 0x00000800 170 171/* DDR_PHY_P0_MPREDQBY0DL3 */ 172DATA 4 0x021b081c 0x33333333 173/* DDR_PHY_P0_MPREDQBY1DL3 */ 174DATA 4 0x021b0820 0x33333333 175/* DDR_PHY_P0_MPREDQBY2DL3 */ 176DATA 4 0x021b0824 0x33333333 177/* DDR_PHY_P0_MPREDQBY3DL3 */ 178DATA 4 0x021b0828 0x33333333 179/* DDR_PHY_P1_MPREDQBY0DL3 */ 180DATA 4 0x021b481c 0x33333333 181/* DDR_PHY_P1_MPREDQBY1DL3 */ 182DATA 4 0x021b4820 0x33333333 183/* DDR_PHY_P1_MPREDQBY2DL3 */ 184DATA 4 0x021b4824 0x33333333 185/* DDR_PHY_P1_MPREDQBY3DL3 */ 186DATA 4 0x021b4828 0x33333333 187 188/* 189 * Read and write data delay, per byte. 190 * For optimized DDR operation it is recommended to run mmdc_calibration 191 * on your board, and replace 4 delay register assigns with resulted values 192 * Note: 193 * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section 194 * should be skipped, or the write/read calibration comming after that 195 * will stall 196 * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. 197 */ 198 199DATA 4 0x021b0848 0x4b4b524f 200DATA 4 0x021b4848 0x494f4c44 201 202DATA 4 0x021b0850 0x3c3d303c 203DATA 4 0x021b4850 0x3c343d38 204 205/*dqs gating dis */ 206DATA 4 0x021b083c 0x20000000 207DATA 4 0x021b0840 0x0 208DATA 4 0x021b483c 0x20000000 209DATA 4 0x021b4840 0x0 210 211/*clk delay */ 212DATA 4 0x021b0858 0xa00 213/*clk delay */ 214DATA 4 0x021b4858 0xa00 215 216/*frc_msr */ 217DATA 4 0x021b08b8 0x00000800 218/*frc_msr */ 219DATA 4 0x021b48b8 0x00000800 220/* Calibration setup end */ 221 222/* Channel0 - startng address 0x80000000 */ 223/* MMDC0_MDCFG0 */ 224DATA 4 0x021b000c 0x34386145 225 226/* MMDC0_MDPDC */ 227DATA 4 0x021b0004 0x00020036 228/* MMDC0_MDCFG1 */ 229DATA 4 0x021b0010 0x00100c83 230/* MMDC0_MDCFG2 */ 231DATA 4 0x021b0014 0x000000Dc 232/* MMDC0_MDMISC */ 233DATA 4 0x021b0018 0x0000174C 234/* MMDC0_MDRWD;*/ 235DATA 4 0x021b002c 0x0f9f26d2 236/* MMDC0_MDOR */ 237DATA 4 0x021b0030 0x0000020e 238/* MMDC0_MDCFG3LP */ 239DATA 4 0x021b0038 0x00190778 240/* MMDC0_MDOTC */ 241DATA 4 0x021b0008 0x00000000 242 243/* CS0_END */ 244DATA 4 0x021b0040 0x0000005f 245/* ROC */ 246DATA 4 0x021b0404 0x0000000f 247 248/* MMDC0_MDCTL */ 249DATA 4 0x021b0000 0xc3010000 250 251/* Channel1 - starting address 0x10000000 */ 252/* MMDC1_MDCFG0 */ 253DATA 4 0x021b400c 0x34386145 254 255/* MMDC1_MDPDC */ 256DATA 4 0x021b4004 0x00020036 257/* MMDC1_MDCFG1 */ 258DATA 4 0x021b4010 0x00100c83 259/* MMDC1_MDCFG2 */ 260DATA 4 0x021b4014 0x000000Dc 261/* MMDC1_MDMISC */ 262DATA 4 0x021b4018 0x0000174C 263/* MMDC1_MDRWD;*/ 264DATA 4 0x021b402c 0x0f9f26d2 265/* MMDC1_MDOR */ 266DATA 4 0x021b4030 0x0000020e 267/* MMDC1_MDCFG3LP */ 268DATA 4 0x021b4038 0x00190778 269/* MMDC1_MDOTC */ 270DATA 4 0x021b4008 0x00000000 271 272/* CS0_END */ 273DATA 4 0x021b4040 0x0000003f 274 275/* MMDC1_MDCTL */ 276DATA 4 0x021b4000 0xc3010000 277 278/* Channel0 : Configure DDR device:*/ 279/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ 280DATA 4 0x021b001c 0x003f8030 281/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ 282DATA 4 0x021b001c 0xff0a8030 283/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ 284DATA 4 0x021b001c 0xa2018030 285/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ 286DATA 4 0x021b001c 0x06028030 287/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ 288DATA 4 0x021b001c 0x01038030 289 290/* Channel1 : Configure DDR device:*/ 291/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ 292DATA 4 0x021b401c 0x003f8030 293/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ 294DATA 4 0x021b401c 0xff0a8030 295/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ 296DATA 4 0x021b401c 0xa2018030 297/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ 298DATA 4 0x021b401c 0x06028030 299/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ 300DATA 4 0x021b401c 0x01038030 301 302/* MMDC0_MDREF */ 303DATA 4 0x021b0020 0x00005800 304/* MMDC1_MDREF */ 305DATA 4 0x021b4020 0x00005800 306 307/* DDR_PHY_P0_MPODTCTRL */ 308DATA 4 0x021b0818 0x0 309/* DDR_PHY_P1_MPODTCTRL */ 310DATA 4 0x021b4818 0x0 311 312/* 313 * calibration values based on calibration compare of 0x00ffff00: 314 * Note, these calibration values are based on Freescale's board 315 * May need to run calibration on target board to fine tune these 316 */ 317 318/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ 319DATA 4 0x021b0800 0xa1310003 320 321/* DDR_PHY_P0_MPMUR0, frc_msr */ 322DATA 4 0x021b08b8 0x00000800 323/* DDR_PHY_P1_MPMUR0, frc_msr */ 324DATA 4 0x021b48b8 0x00000800 325 326/* 327 * MMDC0_MDSCR, clear this register 328 * (especially the configuration bit as initialization is complete) 329 */ 330DATA 4 0x021b001c 0x00000000 331/* 332 * MMDC0_MDSCR, clear this register 333 * (especially the configuration bit as initialization is complete) 334 */ 335DATA 4 0x021b401c 0x00000000 336 337DATA 4 0x020c4068 0x00C03F3F 338DATA 4 0x020c406c 0x0030FC03 339DATA 4 0x020c4070 0x0FFFC000 340DATA 4 0x020c4074 0x3FF00000 341DATA 4 0x020c4078 0x00FFF300 342DATA 4 0x020c407c 0x0F0000C3 343DATA 4 0x020c4080 0x000003FF 344 345DATA 4 0x020e0010 0xF00000CF 346DATA 4 0x020e0018 0x007F007F 347DATA 4 0x020e001c 0x007F007F 348 349#else /* CONFIG_MX6DL_LPDDR2 */ 350 351DATA 4 0x020e0798 0x000c0000 352DATA 4 0x020e0758 0x00000000 353DATA 4 0x020e0588 0x00000030 354DATA 4 0x020e0594 0x00000030 355DATA 4 0x020e056c 0x00000030 356DATA 4 0x020e0578 0x00000030 357DATA 4 0x020e074c 0x00000030 358DATA 4 0x020e057c 0x00000030 359DATA 4 0x020e0590 0x00003000 360DATA 4 0x020e0598 0x00003000 361DATA 4 0x020e058c 0x00000000 362DATA 4 0x020e059c 0x00003030 363DATA 4 0x020e05a0 0x00003030 364DATA 4 0x020e078c 0x00000030 365DATA 4 0x020e0750 0x00020000 366DATA 4 0x020e05a8 0x00000030 367DATA 4 0x020e05b0 0x00000030 368DATA 4 0x020e0524 0x00000030 369DATA 4 0x020e051c 0x00000030 370DATA 4 0x020e0518 0x00000030 371DATA 4 0x020e050c 0x00000030 372DATA 4 0x020e05b8 0x00000030 373DATA 4 0x020e05c0 0x00000030 374DATA 4 0x020e0774 0x00020000 375DATA 4 0x020e0784 0x00000030 376DATA 4 0x020e0788 0x00000030 377DATA 4 0x020e0794 0x00000030 378DATA 4 0x020e079c 0x00000030 379DATA 4 0x020e07a0 0x00000030 380DATA 4 0x020e07a4 0x00000030 381DATA 4 0x020e07a8 0x00000030 382DATA 4 0x020e0748 0x00000030 383DATA 4 0x020e05ac 0x00000030 384DATA 4 0x020e05b4 0x00000030 385DATA 4 0x020e0528 0x00000030 386DATA 4 0x020e0520 0x00000030 387DATA 4 0x020e0514 0x00000030 388DATA 4 0x020e0510 0x00000030 389DATA 4 0x020e05bc 0x00000030 390DATA 4 0x020e05c4 0x00000030 391 392DATA 4 0x021b0800 0xa1390003 393DATA 4 0x021b4800 0xa1390003 394DATA 4 0x021b080c 0x001F001F 395DATA 4 0x021b0810 0x001F001F 396DATA 4 0x021b480c 0x00370037 397DATA 4 0x021b4810 0x00370037 398DATA 4 0x021b083c 0x422f0220 399DATA 4 0x021b0840 0x021f0219 400DATA 4 0x021b483C 0x422f0220 401DATA 4 0x021b4840 0x022d022f 402DATA 4 0x021b0848 0x47494b49 403DATA 4 0x021b4848 0x48484c47 404DATA 4 0x021b0850 0x39382b2f 405DATA 4 0x021b4850 0x2f35312c 406DATA 4 0x021b081c 0x33333333 407DATA 4 0x021b0820 0x33333333 408DATA 4 0x021b0824 0x33333333 409DATA 4 0x021b0828 0x33333333 410DATA 4 0x021b481c 0x33333333 411DATA 4 0x021b4820 0x33333333 412DATA 4 0x021b4824 0x33333333 413DATA 4 0x021b4828 0x33333333 414DATA 4 0x021b08b8 0x00000800 415DATA 4 0x021b48b8 0x00000800 416DATA 4 0x021b0004 0x0002002d 417DATA 4 0x021b0008 0x00333030 418 419DATA 4 0x021b000c 0x40445323 420DATA 4 0x021b0010 0xb66e8c63 421 422DATA 4 0x021b0014 0x01ff00db 423DATA 4 0x021b0018 0x00081740 424DATA 4 0x021b001c 0x00008000 425DATA 4 0x021b002c 0x000026d2 426DATA 4 0x021b0030 0x00440e21 427#ifdef CONFIG_DDR_32BIT 428DATA 4 0x021b0040 0x00000017 429DATA 4 0x021b0000 0xc3190000 430#else 431DATA 4 0x021b0040 0x00000027 432DATA 4 0x021b0000 0xc31a0000 433#endif 434DATA 4 0x021b001c 0x04008032 435DATA 4 0x021b001c 0x0400803a 436DATA 4 0x021b001c 0x00008033 437DATA 4 0x021b001c 0x0000803b 438DATA 4 0x021b001c 0x00428031 439DATA 4 0x021b001c 0x00428039 440DATA 4 0x021b001c 0x07208030 441DATA 4 0x021b001c 0x07208038 442DATA 4 0x021b001c 0x04008040 443DATA 4 0x021b001c 0x04008048 444DATA 4 0x021b0020 0x00005800 445DATA 4 0x021b0818 0x00000007 446DATA 4 0x021b4818 0x00000007 447DATA 4 0x021b0004 0x0002556d 448DATA 4 0x021b4004 0x00011006 449DATA 4 0x021b001c 0x00000000 450 451DATA 4 0x020c4068 0x00C03F3F 452DATA 4 0x020c406c 0x0030FC03 453DATA 4 0x020c4070 0x0FFFC000 454DATA 4 0x020c4074 0x3FF00000 455DATA 4 0x020c4078 0x00FFF300 456DATA 4 0x020c407c 0x0F0000C3 457DATA 4 0x020c4080 0x000003FF 458 459DATA 4 0x020e0010 0xF00000CF 460DATA 4 0x020e0018 0x007F007F 461DATA 4 0x020e001c 0x007F007F 462#endif /* CONFIG_MX6DL_LPDDR2 */ 463