1 /* 2 * (C) Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm/arch/crm_regs.h> 28 #include <asm/arch/clock.h> 29 #include <asm/arch/iomux-mx53.h> 30 #include <asm/errno.h> 31 #include <netdev.h> 32 #include <mmc.h> 33 #include <fsl_esdhc.h> 34 #include <asm/gpio.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 int dram_init(void) 39 { 40 u32 size1, size2; 41 42 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 43 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 44 45 gd->ram_size = size1 + size2; 46 47 return 0; 48 } 49 void dram_init_banksize(void) 50 { 51 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 52 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 53 54 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 55 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 56 } 57 58 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 59 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 60 61 static void setup_iomux_uart(void) 62 { 63 static const iomux_v3_cfg_t uart_pads[] = { 64 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), 65 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), 66 }; 67 68 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 69 } 70 71 static void setup_iomux_fec(void) 72 { 73 static const iomux_v3_cfg_t fec_pads[] = { 74 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 75 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), 76 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 77 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 78 PAD_CTL_HYS | PAD_CTL_PKE), 79 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 80 PAD_CTL_HYS | PAD_CTL_PKE), 81 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 82 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 83 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 84 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 85 PAD_CTL_HYS | PAD_CTL_PKE), 86 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 87 PAD_CTL_HYS | PAD_CTL_PKE), 88 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 89 PAD_CTL_HYS | PAD_CTL_PKE), 90 }; 91 92 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 93 } 94 95 #ifdef CONFIG_FSL_ESDHC 96 struct fsl_esdhc_cfg esdhc_cfg[1] = { 97 {MMC_SDHC1_BASE_ADDR}, 98 }; 99 100 int board_mmc_getcd(struct mmc *mmc) 101 { 102 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); 103 gpio_direction_input(IMX_GPIO_NR(3, 13)); 104 return !gpio_get_value(IMX_GPIO_NR(3, 13)); 105 } 106 107 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 108 PAD_CTL_PUS_100K_UP) 109 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 110 PAD_CTL_DSE_HIGH) 111 112 int board_mmc_init(bd_t *bis) 113 { 114 static const iomux_v3_cfg_t sd1_pads[] = { 115 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 116 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 117 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 118 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 119 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 120 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 121 MX53_PAD_EIM_DA13__GPIO3_13, 122 }; 123 124 u32 index; 125 s32 status = 0; 126 127 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 128 129 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 130 switch (index) { 131 case 0: 132 imx_iomux_v3_setup_multiple_pads(sd1_pads, 133 ARRAY_SIZE(sd1_pads)); 134 break; 135 136 default: 137 printf("Warning: you configured more ESDHC controller" 138 "(%d) as supported by the board(1)\n", 139 CONFIG_SYS_FSL_ESDHC_NUM); 140 return status; 141 } 142 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 143 } 144 145 return status; 146 } 147 #endif 148 149 int board_early_init_f(void) 150 { 151 setup_iomux_uart(); 152 setup_iomux_fec(); 153 154 return 0; 155 } 156 157 int board_init(void) 158 { 159 /* address of boot parameters */ 160 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 161 162 return 0; 163 } 164 165 int checkboard(void) 166 { 167 puts("Board: MX53SMD\n"); 168 169 return 0; 170 } 171