1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/imx-regs.h> 27 #include <asm/arch/mx5x_pins.h> 28 #include <asm/arch/sys_proto.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/iomux.h> 31 #include <asm/arch/clock.h> 32 #include <asm/errno.h> 33 #include <netdev.h> 34 #include <i2c.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <asm/gpio.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 int dram_init(void) 42 { 43 u32 size1, size2; 44 45 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 46 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 47 48 gd->ram_size = size1 + size2; 49 50 return 0; 51 } 52 void dram_init_banksize(void) 53 { 54 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 55 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 56 57 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 58 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 59 } 60 61 static void setup_iomux_uart(void) 62 { 63 /* UART1 RXD */ 64 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); 65 mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 66 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 67 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 68 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 69 PAD_CTL_ODE_OPENDRAIN_ENABLE); 70 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); 71 72 /* UART1 TXD */ 73 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); 74 mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 75 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 76 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 77 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 78 PAD_CTL_ODE_OPENDRAIN_ENABLE); 79 } 80 81 static void setup_iomux_fec(void) 82 { 83 /*FEC_MDIO*/ 84 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); 85 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 86 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 87 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 88 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); 89 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); 90 91 /*FEC_MDC*/ 92 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); 93 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); 94 95 /* FEC RXD1 */ 96 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); 97 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 98 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 99 100 /* FEC RXD0 */ 101 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); 102 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 103 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 104 105 /* FEC TXD1 */ 106 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); 107 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); 108 109 /* FEC TXD0 */ 110 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); 111 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); 112 113 /* FEC TX_EN */ 114 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); 115 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); 116 117 /* FEC TX_CLK */ 118 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); 119 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 120 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 121 122 /* FEC RX_ER */ 123 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); 124 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 125 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 126 127 /* FEC CRS */ 128 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); 129 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 130 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 131 } 132 133 #ifdef CONFIG_FSL_ESDHC 134 struct fsl_esdhc_cfg esdhc_cfg[2] = { 135 {MMC_SDHC1_BASE_ADDR, 1}, 136 {MMC_SDHC3_BASE_ADDR, 1}, 137 }; 138 139 int board_mmc_getcd(u8 *cd, struct mmc *mmc) 140 { 141 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 142 143 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); 144 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); 145 146 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 147 *cd = gpio_get_value(77); /*GPIO3_13*/ 148 else 149 *cd = gpio_get_value(75); /*GPIO3_11*/ 150 151 return 0; 152 } 153 154 int board_mmc_init(bd_t *bis) 155 { 156 u32 index; 157 s32 status = 0; 158 159 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 160 switch (index) { 161 case 0: 162 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); 163 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); 164 mxc_request_iomux(MX53_PIN_SD1_DATA0, 165 IOMUX_CONFIG_ALT0); 166 mxc_request_iomux(MX53_PIN_SD1_DATA1, 167 IOMUX_CONFIG_ALT0); 168 mxc_request_iomux(MX53_PIN_SD1_DATA2, 169 IOMUX_CONFIG_ALT0); 170 mxc_request_iomux(MX53_PIN_SD1_DATA3, 171 IOMUX_CONFIG_ALT0); 172 mxc_request_iomux(MX53_PIN_EIM_DA13, 173 IOMUX_CONFIG_ALT1); 174 175 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 176 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 177 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 178 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 179 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 180 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 181 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 182 PAD_CTL_DRV_HIGH); 183 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 184 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 185 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 186 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 187 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 188 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 189 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 190 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 191 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 192 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 193 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 194 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 195 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 196 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 197 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 198 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 199 break; 200 case 1: 201 mxc_request_iomux(MX53_PIN_ATA_RESET_B, 202 IOMUX_CONFIG_ALT2); 203 mxc_request_iomux(MX53_PIN_ATA_IORDY, 204 IOMUX_CONFIG_ALT2); 205 mxc_request_iomux(MX53_PIN_ATA_DATA8, 206 IOMUX_CONFIG_ALT4); 207 mxc_request_iomux(MX53_PIN_ATA_DATA9, 208 IOMUX_CONFIG_ALT4); 209 mxc_request_iomux(MX53_PIN_ATA_DATA10, 210 IOMUX_CONFIG_ALT4); 211 mxc_request_iomux(MX53_PIN_ATA_DATA11, 212 IOMUX_CONFIG_ALT4); 213 mxc_request_iomux(MX53_PIN_ATA_DATA0, 214 IOMUX_CONFIG_ALT4); 215 mxc_request_iomux(MX53_PIN_ATA_DATA1, 216 IOMUX_CONFIG_ALT4); 217 mxc_request_iomux(MX53_PIN_ATA_DATA2, 218 IOMUX_CONFIG_ALT4); 219 mxc_request_iomux(MX53_PIN_ATA_DATA3, 220 IOMUX_CONFIG_ALT4); 221 mxc_request_iomux(MX53_PIN_EIM_DA11, 222 IOMUX_CONFIG_ALT1); 223 224 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 225 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 226 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 227 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 228 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 229 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 230 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 231 PAD_CTL_DRV_HIGH); 232 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 233 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 234 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 235 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 236 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 237 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 238 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 239 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 240 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 241 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 242 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 243 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 244 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 245 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 246 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 247 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 248 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 249 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 250 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 251 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 252 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 253 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 254 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 255 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 256 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 257 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 258 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 259 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 260 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 261 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 262 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 263 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 264 265 break; 266 default: 267 printf("Warning: you configured more ESDHC controller" 268 "(%d) as supported by the board(2)\n", 269 CONFIG_SYS_FSL_ESDHC_NUM); 270 return status; 271 } 272 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 273 } 274 275 return status; 276 } 277 #endif 278 279 int board_early_init_f(void) 280 { 281 setup_iomux_uart(); 282 setup_iomux_fec(); 283 284 return 0; 285 } 286 287 int board_init(void) 288 { 289 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 290 291 return 0; 292 } 293 294 int checkboard(void) 295 { 296 puts("Board: MX53 LOCO\n"); 297 298 return 0; 299 } 300