1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/imx-regs.h> 27 #include <asm/arch/mx5x_pins.h> 28 #include <asm/arch/sys_proto.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/clock.h> 31 #include <asm/arch/iomux.h> 32 #include <asm/arch/clock.h> 33 #include <asm/errno.h> 34 #include <netdev.h> 35 #include <i2c.h> 36 #include <mmc.h> 37 #include <fsl_esdhc.h> 38 #include <asm/gpio.h> 39 #include <pmic.h> 40 #include <dialog_pmic.h> 41 #include <fsl_pmic.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int dram_init(void) 46 { 47 u32 size1, size2; 48 49 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 50 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 51 52 gd->ram_size = size1 + size2; 53 54 return 0; 55 } 56 void dram_init_banksize(void) 57 { 58 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 59 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 60 61 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 62 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 63 } 64 65 u32 get_board_rev(void) 66 { 67 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 68 struct fuse_bank *bank = &iim->bank[0]; 69 struct fuse_bank0_regs *fuse = 70 (struct fuse_bank0_regs *)bank->fuse_regs; 71 72 int rev = readl(&fuse->gp[6]); 73 74 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 75 } 76 77 static void setup_iomux_uart(void) 78 { 79 /* UART1 RXD */ 80 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); 81 mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 82 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 83 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 84 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 85 PAD_CTL_ODE_OPENDRAIN_ENABLE); 86 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); 87 88 /* UART1 TXD */ 89 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); 90 mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 91 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 92 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 93 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 94 PAD_CTL_ODE_OPENDRAIN_ENABLE); 95 } 96 97 #ifdef CONFIG_USB_EHCI_MX5 98 int board_ehci_hcd_init(int port) 99 { 100 /* request VBUS power enable pin, GPIO7_8 */ 101 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1); 102 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); 103 return 0; 104 } 105 #endif 106 107 static void setup_iomux_fec(void) 108 { 109 /*FEC_MDIO*/ 110 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); 111 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 112 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 113 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 114 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); 115 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); 116 117 /*FEC_MDC*/ 118 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); 119 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); 120 121 /* FEC RXD1 */ 122 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); 123 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 124 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 125 126 /* FEC RXD0 */ 127 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); 128 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 129 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 130 131 /* FEC TXD1 */ 132 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); 133 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); 134 135 /* FEC TXD0 */ 136 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); 137 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); 138 139 /* FEC TX_EN */ 140 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); 141 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); 142 143 /* FEC TX_CLK */ 144 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); 145 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 146 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 147 148 /* FEC RX_ER */ 149 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); 150 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 151 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 152 153 /* FEC CRS */ 154 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); 155 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 156 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 157 } 158 159 #ifdef CONFIG_FSL_ESDHC 160 struct fsl_esdhc_cfg esdhc_cfg[2] = { 161 {MMC_SDHC1_BASE_ADDR, 1}, 162 {MMC_SDHC3_BASE_ADDR, 1}, 163 }; 164 165 int board_mmc_getcd(struct mmc *mmc) 166 { 167 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 168 int ret; 169 170 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); 171 gpio_direction_input(75); 172 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); 173 gpio_direction_input(77); 174 175 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 176 ret = !gpio_get_value(77); /* GPIO3_13 */ 177 else 178 ret = !gpio_get_value(75); /* GPIO3_11 */ 179 180 return ret; 181 } 182 183 int board_mmc_init(bd_t *bis) 184 { 185 u32 index; 186 s32 status = 0; 187 188 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 189 switch (index) { 190 case 0: 191 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); 192 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); 193 mxc_request_iomux(MX53_PIN_SD1_DATA0, 194 IOMUX_CONFIG_ALT0); 195 mxc_request_iomux(MX53_PIN_SD1_DATA1, 196 IOMUX_CONFIG_ALT0); 197 mxc_request_iomux(MX53_PIN_SD1_DATA2, 198 IOMUX_CONFIG_ALT0); 199 mxc_request_iomux(MX53_PIN_SD1_DATA3, 200 IOMUX_CONFIG_ALT0); 201 mxc_request_iomux(MX53_PIN_EIM_DA13, 202 IOMUX_CONFIG_ALT1); 203 204 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 205 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 206 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 207 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 208 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 209 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 210 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 211 PAD_CTL_DRV_HIGH); 212 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 213 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 214 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 215 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 216 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 217 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 218 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 219 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 220 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 221 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 222 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 223 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 224 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 225 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 226 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 227 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 228 break; 229 case 1: 230 mxc_request_iomux(MX53_PIN_ATA_RESET_B, 231 IOMUX_CONFIG_ALT2); 232 mxc_request_iomux(MX53_PIN_ATA_IORDY, 233 IOMUX_CONFIG_ALT2); 234 mxc_request_iomux(MX53_PIN_ATA_DATA8, 235 IOMUX_CONFIG_ALT4); 236 mxc_request_iomux(MX53_PIN_ATA_DATA9, 237 IOMUX_CONFIG_ALT4); 238 mxc_request_iomux(MX53_PIN_ATA_DATA10, 239 IOMUX_CONFIG_ALT4); 240 mxc_request_iomux(MX53_PIN_ATA_DATA11, 241 IOMUX_CONFIG_ALT4); 242 mxc_request_iomux(MX53_PIN_ATA_DATA0, 243 IOMUX_CONFIG_ALT4); 244 mxc_request_iomux(MX53_PIN_ATA_DATA1, 245 IOMUX_CONFIG_ALT4); 246 mxc_request_iomux(MX53_PIN_ATA_DATA2, 247 IOMUX_CONFIG_ALT4); 248 mxc_request_iomux(MX53_PIN_ATA_DATA3, 249 IOMUX_CONFIG_ALT4); 250 mxc_request_iomux(MX53_PIN_EIM_DA11, 251 IOMUX_CONFIG_ALT1); 252 253 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 254 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 255 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 256 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 257 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 258 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 259 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 260 PAD_CTL_DRV_HIGH); 261 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 262 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 263 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 264 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 265 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 266 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 267 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 268 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 269 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 270 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 271 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 272 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 273 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 274 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 275 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 276 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 277 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 278 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 279 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 280 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 281 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 282 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 283 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 284 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 285 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 286 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 287 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 288 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 289 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 290 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 291 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 292 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 293 294 break; 295 default: 296 printf("Warning: you configured more ESDHC controller" 297 "(%d) as supported by the board(2)\n", 298 CONFIG_SYS_FSL_ESDHC_NUM); 299 return status; 300 } 301 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 302 } 303 304 return status; 305 } 306 #endif 307 308 static void setup_iomux_i2c(void) 309 { 310 /* I2C1 SDA */ 311 mxc_request_iomux(MX53_PIN_CSI0_D8, 312 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); 313 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, 314 INPUT_CTL_PATH0); 315 mxc_iomux_set_pad(MX53_PIN_CSI0_D8, 316 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 317 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | 318 PAD_CTL_PUE_PULL | 319 PAD_CTL_ODE_OPENDRAIN_ENABLE); 320 /* I2C1 SCL */ 321 mxc_request_iomux(MX53_PIN_CSI0_D9, 322 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); 323 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, 324 INPUT_CTL_PATH0); 325 mxc_iomux_set_pad(MX53_PIN_CSI0_D9, 326 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 327 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | 328 PAD_CTL_PUE_PULL | 329 PAD_CTL_ODE_OPENDRAIN_ENABLE); 330 } 331 332 static int power_init(void) 333 { 334 unsigned int val; 335 int ret = -1; 336 struct pmic *p; 337 338 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { 339 pmic_dialog_init(); 340 p = get_pmic(); 341 342 /* Set VDDA to 1.25V */ 343 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; 344 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); 345 346 ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); 347 val |= DA9052_SUPPLY_VBCOREGO; 348 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); 349 350 /* Set Vcc peripheral to 1.30V */ 351 ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); 352 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); 353 } 354 355 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { 356 pmic_init(); 357 p = get_pmic(); 358 359 /* Set VDDGP to 1.25V for 1GHz on SW1 */ 360 pmic_reg_read(p, REG_SW_0, &val); 361 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; 362 ret = pmic_reg_write(p, REG_SW_0, val); 363 364 /* Set VCC as 1.30V on SW2 */ 365 pmic_reg_read(p, REG_SW_1, &val); 366 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; 367 ret |= pmic_reg_write(p, REG_SW_1, val); 368 369 /* Set global reset timer to 4s */ 370 pmic_reg_read(p, REG_POWER_CTL2, &val); 371 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; 372 ret |= pmic_reg_write(p, REG_POWER_CTL2, val); 373 374 /* Set VUSBSEL and VUSBEN for USB PHY supply*/ 375 pmic_reg_read(p, REG_MODE_0, &val); 376 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); 377 ret |= pmic_reg_write(p, REG_MODE_0, val); 378 379 /* Set SWBST to 5V in auto mode */ 380 val = SWBST_AUTO; 381 ret |= pmic_reg_write(p, SWBST_CTRL, val); 382 } 383 384 return ret; 385 } 386 387 static void clock_1GHz(void) 388 { 389 int ret; 390 u32 ref_clk = CONFIG_SYS_MX5_HCLK; 391 /* 392 * After increasing voltage to 1.25V, we can switch 393 * CPU clock to 1GHz and DDR to 400MHz safely 394 */ 395 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 396 if (ret) 397 printf("CPU: Switch CPU clock to 1GHZ failed\n"); 398 399 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 400 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 401 if (ret) 402 printf("CPU: Switch DDR clock to 400MHz failed\n"); 403 } 404 405 int board_early_init_f(void) 406 { 407 setup_iomux_uart(); 408 setup_iomux_fec(); 409 410 return 0; 411 } 412 413 int print_cpuinfo(void) 414 { 415 u32 cpurev; 416 417 cpurev = get_cpu_rev(); 418 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", 419 (cpurev & 0xFF000) >> 12, 420 (cpurev & 0x000F0) >> 4, 421 (cpurev & 0x0000F) >> 0, 422 mxc_get_clock(MXC_ARM_CLK) / 1000000); 423 printf("Reset cause: %s\n", get_reset_cause()); 424 return 0; 425 } 426 427 #ifdef CONFIG_BOARD_LATE_INIT 428 int board_late_init(void) 429 { 430 setup_iomux_i2c(); 431 if (!power_init()) 432 clock_1GHz(); 433 print_cpuinfo(); 434 435 return 0; 436 } 437 #endif 438 439 int board_init(void) 440 { 441 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 442 443 mxc_set_sata_internal_clock(); 444 445 return 0; 446 } 447 448 int checkboard(void) 449 { 450 puts("Board: MX53 LOCO\n"); 451 452 return 0; 453 } 454