1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/imx-regs.h> 27 #include <asm/arch/mx5x_pins.h> 28 #include <asm/arch/sys_proto.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/iomux.h> 31 #include <asm/arch/clock.h> 32 #include <asm/errno.h> 33 #include <netdev.h> 34 #include <i2c.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <asm/gpio.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 int dram_init(void) 42 { 43 u32 size1, size2; 44 45 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 46 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 47 48 gd->ram_size = size1 + size2; 49 50 return 0; 51 } 52 void dram_init_banksize(void) 53 { 54 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 55 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 56 57 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 58 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 59 } 60 61 static void setup_iomux_uart(void) 62 { 63 /* UART1 RXD */ 64 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); 65 mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 66 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 67 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 68 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 69 PAD_CTL_ODE_OPENDRAIN_ENABLE); 70 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); 71 72 /* UART1 TXD */ 73 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); 74 mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 75 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 76 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 77 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 78 PAD_CTL_ODE_OPENDRAIN_ENABLE); 79 } 80 81 #ifdef CONFIG_USB_EHCI_MX5 82 int board_ehci_hcd_init(int port) 83 { 84 /* request VBUS power enable pin, GPIO[8}, gpio7 */ 85 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1); 86 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); 87 gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); 88 return 0; 89 } 90 #endif 91 92 static void setup_iomux_fec(void) 93 { 94 /*FEC_MDIO*/ 95 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); 96 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 97 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 98 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 99 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); 100 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); 101 102 /*FEC_MDC*/ 103 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); 104 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); 105 106 /* FEC RXD1 */ 107 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); 108 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 109 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 110 111 /* FEC RXD0 */ 112 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); 113 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 114 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 115 116 /* FEC TXD1 */ 117 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); 118 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); 119 120 /* FEC TXD0 */ 121 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); 122 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); 123 124 /* FEC TX_EN */ 125 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); 126 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); 127 128 /* FEC TX_CLK */ 129 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); 130 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 131 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 132 133 /* FEC RX_ER */ 134 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); 135 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 136 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 137 138 /* FEC CRS */ 139 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); 140 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 141 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 142 } 143 144 #ifdef CONFIG_FSL_ESDHC 145 struct fsl_esdhc_cfg esdhc_cfg[2] = { 146 {MMC_SDHC1_BASE_ADDR, 1}, 147 {MMC_SDHC3_BASE_ADDR, 1}, 148 }; 149 150 int board_mmc_getcd(struct mmc *mmc) 151 { 152 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 153 int ret; 154 155 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); 156 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); 157 158 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 159 ret = !gpio_get_value(77); /* GPIO3_13 */ 160 else 161 ret = !gpio_get_value(75); /* GPIO3_11 */ 162 163 return ret; 164 } 165 166 int board_mmc_init(bd_t *bis) 167 { 168 u32 index; 169 s32 status = 0; 170 171 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 172 switch (index) { 173 case 0: 174 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); 175 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); 176 mxc_request_iomux(MX53_PIN_SD1_DATA0, 177 IOMUX_CONFIG_ALT0); 178 mxc_request_iomux(MX53_PIN_SD1_DATA1, 179 IOMUX_CONFIG_ALT0); 180 mxc_request_iomux(MX53_PIN_SD1_DATA2, 181 IOMUX_CONFIG_ALT0); 182 mxc_request_iomux(MX53_PIN_SD1_DATA3, 183 IOMUX_CONFIG_ALT0); 184 mxc_request_iomux(MX53_PIN_EIM_DA13, 185 IOMUX_CONFIG_ALT1); 186 187 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 188 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 189 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 190 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 191 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 192 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 193 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 194 PAD_CTL_DRV_HIGH); 195 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 196 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 197 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 198 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 199 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 200 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 201 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 202 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 203 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 204 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 205 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 206 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 207 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 208 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 209 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 210 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 211 break; 212 case 1: 213 mxc_request_iomux(MX53_PIN_ATA_RESET_B, 214 IOMUX_CONFIG_ALT2); 215 mxc_request_iomux(MX53_PIN_ATA_IORDY, 216 IOMUX_CONFIG_ALT2); 217 mxc_request_iomux(MX53_PIN_ATA_DATA8, 218 IOMUX_CONFIG_ALT4); 219 mxc_request_iomux(MX53_PIN_ATA_DATA9, 220 IOMUX_CONFIG_ALT4); 221 mxc_request_iomux(MX53_PIN_ATA_DATA10, 222 IOMUX_CONFIG_ALT4); 223 mxc_request_iomux(MX53_PIN_ATA_DATA11, 224 IOMUX_CONFIG_ALT4); 225 mxc_request_iomux(MX53_PIN_ATA_DATA0, 226 IOMUX_CONFIG_ALT4); 227 mxc_request_iomux(MX53_PIN_ATA_DATA1, 228 IOMUX_CONFIG_ALT4); 229 mxc_request_iomux(MX53_PIN_ATA_DATA2, 230 IOMUX_CONFIG_ALT4); 231 mxc_request_iomux(MX53_PIN_ATA_DATA3, 232 IOMUX_CONFIG_ALT4); 233 mxc_request_iomux(MX53_PIN_EIM_DA11, 234 IOMUX_CONFIG_ALT1); 235 236 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 237 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 238 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 239 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 240 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 241 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 242 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 243 PAD_CTL_DRV_HIGH); 244 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 245 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 246 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 247 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 248 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 249 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 250 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 251 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 252 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 253 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 254 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 255 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 256 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 257 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 258 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 259 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 260 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 261 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 262 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 263 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 264 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 265 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 266 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 267 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 268 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 269 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 270 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 271 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 272 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 273 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 274 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 275 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 276 277 break; 278 default: 279 printf("Warning: you configured more ESDHC controller" 280 "(%d) as supported by the board(2)\n", 281 CONFIG_SYS_FSL_ESDHC_NUM); 282 return status; 283 } 284 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 285 } 286 287 return status; 288 } 289 #endif 290 291 int board_early_init_f(void) 292 { 293 setup_iomux_uart(); 294 setup_iomux_fec(); 295 296 return 0; 297 } 298 299 int board_init(void) 300 { 301 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 302 303 return 0; 304 } 305 306 int checkboard(void) 307 { 308 puts("Board: MX53 LOCO\n"); 309 310 return 0; 311 } 312