1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/iomux-mx53.h> 15 #include <asm/arch/clock.h> 16 #include <linux/errno.h> 17 #include <asm/mach-imx/mx5_video.h> 18 #include <netdev.h> 19 #include <i2c.h> 20 #include <input.h> 21 #include <mmc.h> 22 #include <fsl_esdhc.h> 23 #include <asm/gpio.h> 24 #include <power/pmic.h> 25 #include <dialog_pmic.h> 26 #include <fsl_pmic.h> 27 #include <linux/fb.h> 28 #include <ipu_pixfmt.h> 29 30 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 static uint32_t mx53_dram_size[2]; 35 36 phys_size_t get_effective_memsize(void) 37 { 38 /* 39 * WARNING: We must override get_effective_memsize() function here 40 * to report only the size of the first DRAM bank. This is to make 41 * U-Boot relocator place U-Boot into valid memory, that is, at the 42 * end of the first DRAM bank. If we did not override this function 43 * like so, U-Boot would be placed at the address of the first DRAM 44 * bank + total DRAM size - sizeof(uboot), which in the setup where 45 * each DRAM bank contains 512MiB of DRAM would result in placing 46 * U-Boot into invalid memory area close to the end of the first 47 * DRAM bank. 48 */ 49 return mx53_dram_size[0]; 50 } 51 52 int dram_init(void) 53 { 54 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); 55 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); 56 57 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; 58 59 return 0; 60 } 61 62 int dram_init_banksize(void) 63 { 64 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 65 gd->bd->bi_dram[0].size = mx53_dram_size[0]; 66 67 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 68 gd->bd->bi_dram[1].size = mx53_dram_size[1]; 69 70 return 0; 71 } 72 73 u32 get_board_rev(void) 74 { 75 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 76 struct fuse_bank *bank = &iim->bank[0]; 77 struct fuse_bank0_regs *fuse = 78 (struct fuse_bank0_regs *)bank->fuse_regs; 79 80 int rev = readl(&fuse->gp[6]); 81 82 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) 83 rev = 0; 84 85 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 86 } 87 88 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 89 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 90 91 static void setup_iomux_uart(void) 92 { 93 static const iomux_v3_cfg_t uart_pads[] = { 94 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), 95 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), 96 }; 97 98 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 99 } 100 101 #ifdef CONFIG_USB_EHCI_MX5 102 int board_ehci_hcd_init(int port) 103 { 104 /* request VBUS power enable pin, GPIO7_8 */ 105 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); 106 gpio_direction_output(IMX_GPIO_NR(7, 8), 1); 107 return 0; 108 } 109 #endif 110 111 static void setup_iomux_fec(void) 112 { 113 static const iomux_v3_cfg_t fec_pads[] = { 114 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 115 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), 116 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 117 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 118 PAD_CTL_HYS | PAD_CTL_PKE), 119 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 120 PAD_CTL_HYS | PAD_CTL_PKE), 121 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 122 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 123 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 124 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 125 PAD_CTL_HYS | PAD_CTL_PKE), 126 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 127 PAD_CTL_HYS | PAD_CTL_PKE), 128 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 129 PAD_CTL_HYS | PAD_CTL_PKE), 130 }; 131 132 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 133 } 134 135 #ifdef CONFIG_FSL_ESDHC 136 struct fsl_esdhc_cfg esdhc_cfg[2] = { 137 {MMC_SDHC1_BASE_ADDR}, 138 {MMC_SDHC3_BASE_ADDR}, 139 }; 140 141 int board_mmc_getcd(struct mmc *mmc) 142 { 143 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 144 int ret; 145 146 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); 147 gpio_direction_input(IMX_GPIO_NR(3, 11)); 148 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); 149 gpio_direction_input(IMX_GPIO_NR(3, 13)); 150 151 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 152 ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); 153 else 154 ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); 155 156 return ret; 157 } 158 159 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 160 PAD_CTL_PUS_100K_UP) 161 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 162 PAD_CTL_DSE_HIGH) 163 164 int board_mmc_init(bd_t *bis) 165 { 166 static const iomux_v3_cfg_t sd1_pads[] = { 167 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 168 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 169 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 170 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 171 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 172 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 173 MX53_PAD_EIM_DA13__GPIO3_13, 174 }; 175 176 static const iomux_v3_cfg_t sd2_pads[] = { 177 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, 178 SD_CMD_PAD_CTRL), 179 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), 180 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), 181 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), 182 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), 183 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), 184 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), 185 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), 186 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), 187 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), 188 MX53_PAD_EIM_DA11__GPIO3_11, 189 }; 190 191 u32 index; 192 int ret; 193 194 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 195 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 196 197 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 198 switch (index) { 199 case 0: 200 imx_iomux_v3_setup_multiple_pads(sd1_pads, 201 ARRAY_SIZE(sd1_pads)); 202 break; 203 case 1: 204 imx_iomux_v3_setup_multiple_pads(sd2_pads, 205 ARRAY_SIZE(sd2_pads)); 206 break; 207 default: 208 printf("Warning: you configured more ESDHC controller" 209 "(%d) as supported by the board(2)\n", 210 CONFIG_SYS_FSL_ESDHC_NUM); 211 return -EINVAL; 212 } 213 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 214 if (ret) 215 return ret; 216 } 217 218 return 0; 219 } 220 #endif 221 222 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 223 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 224 225 static void setup_iomux_i2c(void) 226 { 227 static const iomux_v3_cfg_t i2c1_pads[] = { 228 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), 229 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), 230 }; 231 232 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); 233 } 234 235 static int power_init(void) 236 { 237 unsigned int val; 238 int ret; 239 struct pmic *p; 240 241 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { 242 ret = pmic_dialog_init(I2C_PMIC); 243 if (ret) 244 return ret; 245 246 p = pmic_get("DIALOG_PMIC"); 247 if (!p) 248 return -ENODEV; 249 250 env_set("fdt_file", "imx53-qsb.dtb"); 251 252 /* Set VDDA to 1.25V */ 253 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; 254 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); 255 if (ret) { 256 printf("Writing to BUCKCORE_REG failed: %d\n", ret); 257 return ret; 258 } 259 260 pmic_reg_read(p, DA9053_SUPPLY_REG, &val); 261 val |= DA9052_SUPPLY_VBCOREGO; 262 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); 263 if (ret) { 264 printf("Writing to SUPPLY_REG failed: %d\n", ret); 265 return ret; 266 } 267 268 /* Set Vcc peripheral to 1.30V */ 269 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); 270 if (ret) { 271 printf("Writing to BUCKPRO_REG failed: %d\n", ret); 272 return ret; 273 } 274 275 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); 276 if (ret) { 277 printf("Writing to SUPPLY_REG failed: %d\n", ret); 278 return ret; 279 } 280 281 return ret; 282 } 283 284 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { 285 ret = pmic_init(I2C_0); 286 if (ret) 287 return ret; 288 289 p = pmic_get("FSL_PMIC"); 290 if (!p) 291 return -ENODEV; 292 293 env_set("fdt_file", "imx53-qsrb.dtb"); 294 295 /* Set VDDGP to 1.25V for 1GHz on SW1 */ 296 pmic_reg_read(p, REG_SW_0, &val); 297 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; 298 ret = pmic_reg_write(p, REG_SW_0, val); 299 if (ret) { 300 printf("Writing to REG_SW_0 failed: %d\n", ret); 301 return ret; 302 } 303 304 /* Set VCC as 1.30V on SW2 */ 305 pmic_reg_read(p, REG_SW_1, &val); 306 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; 307 ret = pmic_reg_write(p, REG_SW_1, val); 308 if (ret) { 309 printf("Writing to REG_SW_1 failed: %d\n", ret); 310 return ret; 311 } 312 313 /* Set global reset timer to 4s */ 314 pmic_reg_read(p, REG_POWER_CTL2, &val); 315 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; 316 ret = pmic_reg_write(p, REG_POWER_CTL2, val); 317 if (ret) { 318 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); 319 return ret; 320 } 321 322 /* Set VUSBSEL and VUSBEN for USB PHY supply*/ 323 pmic_reg_read(p, REG_MODE_0, &val); 324 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); 325 ret = pmic_reg_write(p, REG_MODE_0, val); 326 if (ret) { 327 printf("Writing to REG_MODE_0 failed: %d\n", ret); 328 return ret; 329 } 330 331 /* Set SWBST to 5V in auto mode */ 332 val = SWBST_AUTO; 333 ret = pmic_reg_write(p, SWBST_CTRL, val); 334 if (ret) { 335 printf("Writing to SWBST_CTRL failed: %d\n", ret); 336 return ret; 337 } 338 339 return ret; 340 } 341 342 return -1; 343 } 344 345 static void clock_1GHz(void) 346 { 347 int ret; 348 u32 ref_clk = MXC_HCLK; 349 /* 350 * After increasing voltage to 1.25V, we can switch 351 * CPU clock to 1GHz and DDR to 400MHz safely 352 */ 353 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 354 if (ret) 355 printf("CPU: Switch CPU clock to 1GHZ failed\n"); 356 357 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 358 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 359 if (ret) 360 printf("CPU: Switch DDR clock to 400MHz failed\n"); 361 } 362 363 int board_early_init_f(void) 364 { 365 setup_iomux_uart(); 366 setup_iomux_fec(); 367 setup_iomux_lcd(); 368 369 return 0; 370 } 371 372 /* 373 * Do not overwrite the console 374 * Use always serial for U-Boot console 375 */ 376 int overwrite_console(void) 377 { 378 return 1; 379 } 380 381 int board_init(void) 382 { 383 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 384 385 mxc_set_sata_internal_clock(); 386 setup_iomux_i2c(); 387 388 return 0; 389 } 390 391 int board_late_init(void) 392 { 393 if (!power_init()) 394 clock_1GHz(); 395 396 return 0; 397 } 398 399 int checkboard(void) 400 { 401 puts("Board: MX53 LOCO\n"); 402 403 return 0; 404 } 405