1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/imx-regs.h> 27 #include <asm/arch/mx5x_pins.h> 28 #include <asm/arch/sys_proto.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/clock.h> 31 #include <asm/arch/iomux.h> 32 #include <asm/arch/clock.h> 33 #include <asm/errno.h> 34 #include <netdev.h> 35 #include <i2c.h> 36 #include <mmc.h> 37 #include <fsl_esdhc.h> 38 #include <asm/gpio.h> 39 #include <pmic.h> 40 #include <dialog_pmic.h> 41 #include <fsl_pmic.h> 42 #include <linux/fb.h> 43 #include <ipu_pixfmt.h> 44 45 #define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */ 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 int dram_init(void) 50 { 51 u32 size1, size2; 52 53 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 54 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 55 56 gd->ram_size = size1 + size2; 57 58 return 0; 59 } 60 void dram_init_banksize(void) 61 { 62 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 63 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 64 65 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 66 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 67 } 68 69 u32 get_board_rev(void) 70 { 71 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 72 struct fuse_bank *bank = &iim->bank[0]; 73 struct fuse_bank0_regs *fuse = 74 (struct fuse_bank0_regs *)bank->fuse_regs; 75 76 int rev = readl(&fuse->gp[6]); 77 78 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) 79 rev = 0; 80 81 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 82 } 83 84 static void setup_iomux_uart(void) 85 { 86 /* UART1 RXD */ 87 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); 88 mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 89 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 90 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 91 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 92 PAD_CTL_ODE_OPENDRAIN_ENABLE); 93 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); 94 95 /* UART1 TXD */ 96 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); 97 mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 98 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 99 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 100 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 101 PAD_CTL_ODE_OPENDRAIN_ENABLE); 102 } 103 104 #ifdef CONFIG_USB_EHCI_MX5 105 int board_ehci_hcd_init(int port) 106 { 107 /* request VBUS power enable pin, GPIO7_8 */ 108 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1); 109 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); 110 return 0; 111 } 112 #endif 113 114 static void setup_iomux_fec(void) 115 { 116 /*FEC_MDIO*/ 117 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); 118 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 119 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 120 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 121 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); 122 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); 123 124 /*FEC_MDC*/ 125 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); 126 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); 127 128 /* FEC RXD1 */ 129 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); 130 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 131 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 132 133 /* FEC RXD0 */ 134 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); 135 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 136 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 137 138 /* FEC TXD1 */ 139 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); 140 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); 141 142 /* FEC TXD0 */ 143 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); 144 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); 145 146 /* FEC TX_EN */ 147 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); 148 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); 149 150 /* FEC TX_CLK */ 151 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); 152 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 153 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 154 155 /* FEC RX_ER */ 156 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); 157 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 158 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 159 160 /* FEC CRS */ 161 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); 162 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 163 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 164 } 165 166 #ifdef CONFIG_FSL_ESDHC 167 struct fsl_esdhc_cfg esdhc_cfg[2] = { 168 {MMC_SDHC1_BASE_ADDR, 1}, 169 {MMC_SDHC3_BASE_ADDR, 1}, 170 }; 171 172 int board_mmc_getcd(struct mmc *mmc) 173 { 174 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 175 int ret; 176 177 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); 178 gpio_direction_input(75); 179 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); 180 gpio_direction_input(77); 181 182 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 183 ret = !gpio_get_value(77); /* GPIO3_13 */ 184 else 185 ret = !gpio_get_value(75); /* GPIO3_11 */ 186 187 return ret; 188 } 189 190 int board_mmc_init(bd_t *bis) 191 { 192 u32 index; 193 s32 status = 0; 194 195 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 196 switch (index) { 197 case 0: 198 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); 199 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); 200 mxc_request_iomux(MX53_PIN_SD1_DATA0, 201 IOMUX_CONFIG_ALT0); 202 mxc_request_iomux(MX53_PIN_SD1_DATA1, 203 IOMUX_CONFIG_ALT0); 204 mxc_request_iomux(MX53_PIN_SD1_DATA2, 205 IOMUX_CONFIG_ALT0); 206 mxc_request_iomux(MX53_PIN_SD1_DATA3, 207 IOMUX_CONFIG_ALT0); 208 mxc_request_iomux(MX53_PIN_EIM_DA13, 209 IOMUX_CONFIG_ALT1); 210 211 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 212 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 213 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 214 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 215 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 216 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 217 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 218 PAD_CTL_DRV_HIGH); 219 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 220 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 221 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 222 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 223 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 224 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 225 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 226 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 227 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 228 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 229 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 230 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 231 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 232 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 233 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 234 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 235 break; 236 case 1: 237 mxc_request_iomux(MX53_PIN_ATA_RESET_B, 238 IOMUX_CONFIG_ALT2); 239 mxc_request_iomux(MX53_PIN_ATA_IORDY, 240 IOMUX_CONFIG_ALT2); 241 mxc_request_iomux(MX53_PIN_ATA_DATA8, 242 IOMUX_CONFIG_ALT4); 243 mxc_request_iomux(MX53_PIN_ATA_DATA9, 244 IOMUX_CONFIG_ALT4); 245 mxc_request_iomux(MX53_PIN_ATA_DATA10, 246 IOMUX_CONFIG_ALT4); 247 mxc_request_iomux(MX53_PIN_ATA_DATA11, 248 IOMUX_CONFIG_ALT4); 249 mxc_request_iomux(MX53_PIN_ATA_DATA0, 250 IOMUX_CONFIG_ALT4); 251 mxc_request_iomux(MX53_PIN_ATA_DATA1, 252 IOMUX_CONFIG_ALT4); 253 mxc_request_iomux(MX53_PIN_ATA_DATA2, 254 IOMUX_CONFIG_ALT4); 255 mxc_request_iomux(MX53_PIN_ATA_DATA3, 256 IOMUX_CONFIG_ALT4); 257 mxc_request_iomux(MX53_PIN_EIM_DA11, 258 IOMUX_CONFIG_ALT1); 259 260 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 261 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 262 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 263 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 264 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 265 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 266 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 267 PAD_CTL_DRV_HIGH); 268 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 269 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 270 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 271 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 272 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 273 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 274 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 275 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 276 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 277 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 278 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 279 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 280 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 281 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 282 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 283 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 284 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 285 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 286 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 287 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 288 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 289 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 290 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 291 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 292 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 293 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 294 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 295 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 296 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 297 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 298 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 299 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 300 301 break; 302 default: 303 printf("Warning: you configured more ESDHC controller" 304 "(%d) as supported by the board(2)\n", 305 CONFIG_SYS_FSL_ESDHC_NUM); 306 return status; 307 } 308 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 309 } 310 311 return status; 312 } 313 #endif 314 315 static void setup_iomux_i2c(void) 316 { 317 /* I2C1 SDA */ 318 mxc_request_iomux(MX53_PIN_CSI0_D8, 319 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); 320 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, 321 INPUT_CTL_PATH0); 322 mxc_iomux_set_pad(MX53_PIN_CSI0_D8, 323 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 324 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | 325 PAD_CTL_PUE_PULL | 326 PAD_CTL_ODE_OPENDRAIN_ENABLE); 327 /* I2C1 SCL */ 328 mxc_request_iomux(MX53_PIN_CSI0_D9, 329 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); 330 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, 331 INPUT_CTL_PATH0); 332 mxc_iomux_set_pad(MX53_PIN_CSI0_D9, 333 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 334 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | 335 PAD_CTL_PUE_PULL | 336 PAD_CTL_ODE_OPENDRAIN_ENABLE); 337 } 338 339 static int power_init(void) 340 { 341 unsigned int val; 342 int ret = -1; 343 struct pmic *p; 344 345 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { 346 pmic_dialog_init(); 347 p = get_pmic(); 348 349 /* Set VDDA to 1.25V */ 350 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; 351 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); 352 353 ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); 354 val |= DA9052_SUPPLY_VBCOREGO; 355 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); 356 357 /* Set Vcc peripheral to 1.30V */ 358 ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); 359 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); 360 } 361 362 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { 363 pmic_init(); 364 p = get_pmic(); 365 366 /* Set VDDGP to 1.25V for 1GHz on SW1 */ 367 pmic_reg_read(p, REG_SW_0, &val); 368 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; 369 ret = pmic_reg_write(p, REG_SW_0, val); 370 371 /* Set VCC as 1.30V on SW2 */ 372 pmic_reg_read(p, REG_SW_1, &val); 373 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; 374 ret |= pmic_reg_write(p, REG_SW_1, val); 375 376 /* Set global reset timer to 4s */ 377 pmic_reg_read(p, REG_POWER_CTL2, &val); 378 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; 379 ret |= pmic_reg_write(p, REG_POWER_CTL2, val); 380 381 /* Set VUSBSEL and VUSBEN for USB PHY supply*/ 382 pmic_reg_read(p, REG_MODE_0, &val); 383 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); 384 ret |= pmic_reg_write(p, REG_MODE_0, val); 385 386 /* Set SWBST to 5V in auto mode */ 387 val = SWBST_AUTO; 388 ret |= pmic_reg_write(p, SWBST_CTRL, val); 389 } 390 391 return ret; 392 } 393 394 static void clock_1GHz(void) 395 { 396 int ret; 397 u32 ref_clk = CONFIG_SYS_MX5_HCLK; 398 /* 399 * After increasing voltage to 1.25V, we can switch 400 * CPU clock to 1GHz and DDR to 400MHz safely 401 */ 402 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 403 if (ret) 404 printf("CPU: Switch CPU clock to 1GHZ failed\n"); 405 406 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 407 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 408 if (ret) 409 printf("CPU: Switch DDR clock to 400MHz failed\n"); 410 } 411 412 static struct fb_videomode claa_wvga = { 413 .name = "CLAA07LC0ACW", 414 .refresh = 57, 415 .xres = 800, 416 .yres = 480, 417 .pixclock = 37037, 418 .left_margin = 40, 419 .right_margin = 60, 420 .upper_margin = 10, 421 .lower_margin = 10, 422 .hsync_len = 20, 423 .vsync_len = 10, 424 .sync = 0, 425 .vmode = FB_VMODE_NONINTERLACED 426 }; 427 428 void lcd_iomux(void) 429 { 430 mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0); 431 mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0); 432 mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0); 433 mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0); 434 mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0); 435 mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0); 436 mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0); 437 mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0); 438 mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0); 439 mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0); 440 mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0); 441 mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0); 442 mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0); 443 mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0); 444 mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0); 445 mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0); 446 mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0); 447 mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0); 448 mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0); 449 mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0); 450 mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0); 451 mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0); 452 mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0); 453 mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0); 454 mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0); 455 mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0); 456 mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0); 457 mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0); 458 459 /* Turn on GPIO backlight */ 460 mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1); 461 gpio_direction_output(MX53LOCO_LCD_POWER, 1); 462 463 /* Turn on display contrast */ 464 mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); 465 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1); 466 } 467 468 void lcd_enable(void) 469 { 470 int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565); 471 if (ret) 472 printf("LCD cannot be configured: %d\n", ret); 473 } 474 475 int board_early_init_f(void) 476 { 477 setup_iomux_uart(); 478 setup_iomux_fec(); 479 lcd_iomux(); 480 481 return 0; 482 } 483 484 int print_cpuinfo(void) 485 { 486 u32 cpurev; 487 488 cpurev = get_cpu_rev(); 489 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", 490 (cpurev & 0xFF000) >> 12, 491 (cpurev & 0x000F0) >> 4, 492 (cpurev & 0x0000F) >> 0, 493 mxc_get_clock(MXC_ARM_CLK) / 1000000); 494 printf("Reset cause: %s\n", get_reset_cause()); 495 return 0; 496 } 497 498 /* 499 * Do not overwrite the console 500 * Use always serial for U-Boot console 501 */ 502 int overwrite_console(void) 503 { 504 return 1; 505 } 506 507 int board_init(void) 508 { 509 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 510 511 mxc_set_sata_internal_clock(); 512 setup_iomux_i2c(); 513 if (!power_init()) 514 clock_1GHz(); 515 print_cpuinfo(); 516 517 lcd_enable(); 518 519 return 0; 520 } 521 522 int checkboard(void) 523 { 524 puts("Board: MX53 LOCO\n"); 525 526 return 0; 527 } 528