1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/imx-regs.h> 27 #include <asm/arch/sys_proto.h> 28 #include <asm/arch/crm_regs.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch/iomux-mx53.h> 31 #include <asm/arch/clock.h> 32 #include <asm/errno.h> 33 #include <asm/imx-common/mx5_video.h> 34 #include <netdev.h> 35 #include <i2c.h> 36 #include <mmc.h> 37 #include <fsl_esdhc.h> 38 #include <asm/gpio.h> 39 #include <power/pmic.h> 40 #include <dialog_pmic.h> 41 #include <fsl_pmic.h> 42 #include <linux/fb.h> 43 #include <ipu_pixfmt.h> 44 45 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 int dram_init(void) 50 { 51 u32 size1, size2; 52 53 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 54 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 55 56 gd->ram_size = size1 + size2; 57 58 return 0; 59 } 60 void dram_init_banksize(void) 61 { 62 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 63 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 64 65 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 66 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 67 } 68 69 u32 get_board_rev(void) 70 { 71 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 72 struct fuse_bank *bank = &iim->bank[0]; 73 struct fuse_bank0_regs *fuse = 74 (struct fuse_bank0_regs *)bank->fuse_regs; 75 76 int rev = readl(&fuse->gp[6]); 77 78 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) 79 rev = 0; 80 81 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 82 } 83 84 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 85 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 86 87 static void setup_iomux_uart(void) 88 { 89 static const iomux_v3_cfg_t uart_pads[] = { 90 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), 91 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), 92 }; 93 94 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 95 } 96 97 #ifdef CONFIG_USB_EHCI_MX5 98 int board_ehci_hcd_init(int port) 99 { 100 /* request VBUS power enable pin, GPIO7_8 */ 101 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); 102 gpio_direction_output(IMX_GPIO_NR(7, 8), 1); 103 return 0; 104 } 105 #endif 106 107 static void setup_iomux_fec(void) 108 { 109 static const iomux_v3_cfg_t fec_pads[] = { 110 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 111 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), 112 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 113 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 114 PAD_CTL_HYS | PAD_CTL_PKE), 115 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 116 PAD_CTL_HYS | PAD_CTL_PKE), 117 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 118 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 119 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 120 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 121 PAD_CTL_HYS | PAD_CTL_PKE), 122 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 123 PAD_CTL_HYS | PAD_CTL_PKE), 124 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 125 PAD_CTL_HYS | PAD_CTL_PKE), 126 }; 127 128 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 129 } 130 131 #ifdef CONFIG_FSL_ESDHC 132 struct fsl_esdhc_cfg esdhc_cfg[2] = { 133 {MMC_SDHC1_BASE_ADDR}, 134 {MMC_SDHC3_BASE_ADDR}, 135 }; 136 137 int board_mmc_getcd(struct mmc *mmc) 138 { 139 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 140 int ret; 141 142 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); 143 gpio_direction_input(IMX_GPIO_NR(3, 11)); 144 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); 145 gpio_direction_input(IMX_GPIO_NR(3, 13)); 146 147 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 148 ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); 149 else 150 ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); 151 152 return ret; 153 } 154 155 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 156 PAD_CTL_PUS_100K_UP) 157 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 158 PAD_CTL_DSE_HIGH) 159 160 int board_mmc_init(bd_t *bis) 161 { 162 static const iomux_v3_cfg_t sd1_pads[] = { 163 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 164 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 165 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 166 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 167 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 168 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 169 MX53_PAD_EIM_DA13__GPIO3_13, 170 }; 171 172 static const iomux_v3_cfg_t sd2_pads[] = { 173 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, 174 SD_CMD_PAD_CTRL), 175 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), 176 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), 177 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), 178 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), 179 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), 180 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), 181 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), 182 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), 183 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), 184 MX53_PAD_EIM_DA11__GPIO3_11, 185 }; 186 187 u32 index; 188 s32 status = 0; 189 190 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 191 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 192 193 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 194 switch (index) { 195 case 0: 196 imx_iomux_v3_setup_multiple_pads(sd1_pads, 197 ARRAY_SIZE(sd1_pads)); 198 break; 199 case 1: 200 imx_iomux_v3_setup_multiple_pads(sd2_pads, 201 ARRAY_SIZE(sd2_pads)); 202 break; 203 default: 204 printf("Warning: you configured more ESDHC controller" 205 "(%d) as supported by the board(2)\n", 206 CONFIG_SYS_FSL_ESDHC_NUM); 207 return status; 208 } 209 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 210 } 211 212 return status; 213 } 214 #endif 215 216 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 217 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 218 219 static void setup_iomux_i2c(void) 220 { 221 static const iomux_v3_cfg_t i2c1_pads[] = { 222 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), 223 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), 224 }; 225 226 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); 227 } 228 229 static int power_init(void) 230 { 231 unsigned int val; 232 int ret; 233 struct pmic *p; 234 235 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { 236 ret = pmic_dialog_init(I2C_PMIC); 237 if (ret) 238 return ret; 239 240 p = pmic_get("DIALOG_PMIC"); 241 if (!p) 242 return -ENODEV; 243 244 /* Set VDDA to 1.25V */ 245 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; 246 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); 247 if (ret) { 248 printf("Writing to BUCKCORE_REG failed: %d\n", ret); 249 return ret; 250 } 251 252 pmic_reg_read(p, DA9053_SUPPLY_REG, &val); 253 val |= DA9052_SUPPLY_VBCOREGO; 254 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); 255 if (ret) { 256 printf("Writing to SUPPLY_REG failed: %d\n", ret); 257 return ret; 258 } 259 260 /* Set Vcc peripheral to 1.30V */ 261 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); 262 if (ret) { 263 printf("Writing to BUCKPRO_REG failed: %d\n", ret); 264 return ret; 265 } 266 267 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); 268 if (ret) { 269 printf("Writing to SUPPLY_REG failed: %d\n", ret); 270 return ret; 271 } 272 273 return ret; 274 } 275 276 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { 277 ret = pmic_init(I2C_PMIC); 278 if (ret) 279 return ret; 280 281 p = pmic_get("FSL_PMIC"); 282 if (!p) 283 return -ENODEV; 284 285 /* Set VDDGP to 1.25V for 1GHz on SW1 */ 286 pmic_reg_read(p, REG_SW_0, &val); 287 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; 288 ret = pmic_reg_write(p, REG_SW_0, val); 289 if (ret) { 290 printf("Writing to REG_SW_0 failed: %d\n", ret); 291 return ret; 292 } 293 294 /* Set VCC as 1.30V on SW2 */ 295 pmic_reg_read(p, REG_SW_1, &val); 296 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; 297 ret = pmic_reg_write(p, REG_SW_1, val); 298 if (ret) { 299 printf("Writing to REG_SW_1 failed: %d\n", ret); 300 return ret; 301 } 302 303 /* Set global reset timer to 4s */ 304 pmic_reg_read(p, REG_POWER_CTL2, &val); 305 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; 306 ret = pmic_reg_write(p, REG_POWER_CTL2, val); 307 if (ret) { 308 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); 309 return ret; 310 } 311 312 /* Set VUSBSEL and VUSBEN for USB PHY supply*/ 313 pmic_reg_read(p, REG_MODE_0, &val); 314 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); 315 ret = pmic_reg_write(p, REG_MODE_0, val); 316 if (ret) { 317 printf("Writing to REG_MODE_0 failed: %d\n", ret); 318 return ret; 319 } 320 321 /* Set SWBST to 5V in auto mode */ 322 val = SWBST_AUTO; 323 ret = pmic_reg_write(p, SWBST_CTRL, val); 324 if (ret) { 325 printf("Writing to SWBST_CTRL failed: %d\n", ret); 326 return ret; 327 } 328 329 return ret; 330 } 331 332 return -1; 333 } 334 335 static void clock_1GHz(void) 336 { 337 int ret; 338 u32 ref_clk = MXC_HCLK; 339 /* 340 * After increasing voltage to 1.25V, we can switch 341 * CPU clock to 1GHz and DDR to 400MHz safely 342 */ 343 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 344 if (ret) 345 printf("CPU: Switch CPU clock to 1GHZ failed\n"); 346 347 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 348 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 349 if (ret) 350 printf("CPU: Switch DDR clock to 400MHz failed\n"); 351 } 352 353 int board_early_init_f(void) 354 { 355 setup_iomux_uart(); 356 setup_iomux_fec(); 357 setup_iomux_lcd(); 358 359 return 0; 360 } 361 362 int print_cpuinfo(void) 363 { 364 u32 cpurev; 365 366 cpurev = get_cpu_rev(); 367 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", 368 (cpurev & 0xFF000) >> 12, 369 (cpurev & 0x000F0) >> 4, 370 (cpurev & 0x0000F) >> 0, 371 mxc_get_clock(MXC_ARM_CLK) / 1000000); 372 printf("Reset cause: %s\n", get_reset_cause()); 373 return 0; 374 } 375 376 /* 377 * Do not overwrite the console 378 * Use always serial for U-Boot console 379 */ 380 int overwrite_console(void) 381 { 382 return 1; 383 } 384 385 int board_init(void) 386 { 387 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 388 389 mxc_set_sata_internal_clock(); 390 setup_iomux_i2c(); 391 392 return 0; 393 } 394 395 int board_late_init(void) 396 { 397 if (!power_init()) 398 clock_1GHz(); 399 print_cpuinfo(); 400 401 return 0; 402 } 403 404 int checkboard(void) 405 { 406 puts("Board: MX53 LOCO\n"); 407 408 return 0; 409 } 410