1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/iomux-mx53.h> 15 #include <asm/arch/clock.h> 16 #include <linux/errno.h> 17 #include <asm/mach-imx/mx5_video.h> 18 #include <netdev.h> 19 #include <i2c.h> 20 #include <mmc.h> 21 #include <fsl_esdhc.h> 22 #include <asm/gpio.h> 23 #include <power/pmic.h> 24 #include <dialog_pmic.h> 25 #include <fsl_pmic.h> 26 #include <linux/fb.h> 27 #include <ipu_pixfmt.h> 28 29 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 static uint32_t mx53_dram_size[2]; 34 35 phys_size_t get_effective_memsize(void) 36 { 37 /* 38 * WARNING: We must override get_effective_memsize() function here 39 * to report only the size of the first DRAM bank. This is to make 40 * U-Boot relocator place U-Boot into valid memory, that is, at the 41 * end of the first DRAM bank. If we did not override this function 42 * like so, U-Boot would be placed at the address of the first DRAM 43 * bank + total DRAM size - sizeof(uboot), which in the setup where 44 * each DRAM bank contains 512MiB of DRAM would result in placing 45 * U-Boot into invalid memory area close to the end of the first 46 * DRAM bank. 47 */ 48 return mx53_dram_size[0]; 49 } 50 51 int dram_init(void) 52 { 53 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); 54 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); 55 56 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; 57 58 return 0; 59 } 60 61 int dram_init_banksize(void) 62 { 63 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 64 gd->bd->bi_dram[0].size = mx53_dram_size[0]; 65 66 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 67 gd->bd->bi_dram[1].size = mx53_dram_size[1]; 68 69 return 0; 70 } 71 72 u32 get_board_rev(void) 73 { 74 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 75 struct fuse_bank *bank = &iim->bank[0]; 76 struct fuse_bank0_regs *fuse = 77 (struct fuse_bank0_regs *)bank->fuse_regs; 78 79 int rev = readl(&fuse->gp[6]); 80 81 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) 82 rev = 0; 83 84 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 85 } 86 87 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 88 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 89 90 static void setup_iomux_uart(void) 91 { 92 static const iomux_v3_cfg_t uart_pads[] = { 93 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), 94 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), 95 }; 96 97 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 98 } 99 100 #ifdef CONFIG_USB_EHCI_MX5 101 int board_ehci_hcd_init(int port) 102 { 103 /* request VBUS power enable pin, GPIO7_8 */ 104 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); 105 gpio_direction_output(IMX_GPIO_NR(7, 8), 1); 106 return 0; 107 } 108 #endif 109 110 static void setup_iomux_fec(void) 111 { 112 static const iomux_v3_cfg_t fec_pads[] = { 113 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 114 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), 115 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 116 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 117 PAD_CTL_HYS | PAD_CTL_PKE), 118 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 119 PAD_CTL_HYS | PAD_CTL_PKE), 120 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 121 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 122 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 123 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 124 PAD_CTL_HYS | PAD_CTL_PKE), 125 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 126 PAD_CTL_HYS | PAD_CTL_PKE), 127 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 128 PAD_CTL_HYS | PAD_CTL_PKE), 129 }; 130 131 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 132 } 133 134 #ifdef CONFIG_FSL_ESDHC 135 struct fsl_esdhc_cfg esdhc_cfg[2] = { 136 {MMC_SDHC1_BASE_ADDR}, 137 {MMC_SDHC3_BASE_ADDR}, 138 }; 139 140 int board_mmc_getcd(struct mmc *mmc) 141 { 142 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 143 int ret; 144 145 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); 146 gpio_direction_input(IMX_GPIO_NR(3, 11)); 147 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); 148 gpio_direction_input(IMX_GPIO_NR(3, 13)); 149 150 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 151 ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); 152 else 153 ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); 154 155 return ret; 156 } 157 158 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 159 PAD_CTL_PUS_100K_UP) 160 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 161 PAD_CTL_DSE_HIGH) 162 163 int board_mmc_init(bd_t *bis) 164 { 165 static const iomux_v3_cfg_t sd1_pads[] = { 166 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 167 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 168 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 169 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 170 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 171 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 172 MX53_PAD_EIM_DA13__GPIO3_13, 173 }; 174 175 static const iomux_v3_cfg_t sd2_pads[] = { 176 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, 177 SD_CMD_PAD_CTRL), 178 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), 179 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), 180 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), 181 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), 182 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), 183 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), 184 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), 185 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), 186 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), 187 MX53_PAD_EIM_DA11__GPIO3_11, 188 }; 189 190 u32 index; 191 int ret; 192 193 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 194 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 195 196 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 197 switch (index) { 198 case 0: 199 imx_iomux_v3_setup_multiple_pads(sd1_pads, 200 ARRAY_SIZE(sd1_pads)); 201 break; 202 case 1: 203 imx_iomux_v3_setup_multiple_pads(sd2_pads, 204 ARRAY_SIZE(sd2_pads)); 205 break; 206 default: 207 printf("Warning: you configured more ESDHC controller" 208 "(%d) as supported by the board(2)\n", 209 CONFIG_SYS_FSL_ESDHC_NUM); 210 return -EINVAL; 211 } 212 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 213 if (ret) 214 return ret; 215 } 216 217 return 0; 218 } 219 #endif 220 221 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 222 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 223 224 static void setup_iomux_i2c(void) 225 { 226 static const iomux_v3_cfg_t i2c1_pads[] = { 227 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), 228 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), 229 }; 230 231 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); 232 } 233 234 static int power_init(void) 235 { 236 unsigned int val; 237 int ret; 238 struct pmic *p; 239 240 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { 241 ret = pmic_dialog_init(I2C_PMIC); 242 if (ret) 243 return ret; 244 245 p = pmic_get("DIALOG_PMIC"); 246 if (!p) 247 return -ENODEV; 248 249 setenv("fdt_file", "imx53-qsb.dtb"); 250 251 /* Set VDDA to 1.25V */ 252 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; 253 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); 254 if (ret) { 255 printf("Writing to BUCKCORE_REG failed: %d\n", ret); 256 return ret; 257 } 258 259 pmic_reg_read(p, DA9053_SUPPLY_REG, &val); 260 val |= DA9052_SUPPLY_VBCOREGO; 261 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); 262 if (ret) { 263 printf("Writing to SUPPLY_REG failed: %d\n", ret); 264 return ret; 265 } 266 267 /* Set Vcc peripheral to 1.30V */ 268 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); 269 if (ret) { 270 printf("Writing to BUCKPRO_REG failed: %d\n", ret); 271 return ret; 272 } 273 274 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); 275 if (ret) { 276 printf("Writing to SUPPLY_REG failed: %d\n", ret); 277 return ret; 278 } 279 280 return ret; 281 } 282 283 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { 284 ret = pmic_init(I2C_0); 285 if (ret) 286 return ret; 287 288 p = pmic_get("FSL_PMIC"); 289 if (!p) 290 return -ENODEV; 291 292 setenv("fdt_file", "imx53-qsrb.dtb"); 293 294 /* Set VDDGP to 1.25V for 1GHz on SW1 */ 295 pmic_reg_read(p, REG_SW_0, &val); 296 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; 297 ret = pmic_reg_write(p, REG_SW_0, val); 298 if (ret) { 299 printf("Writing to REG_SW_0 failed: %d\n", ret); 300 return ret; 301 } 302 303 /* Set VCC as 1.30V on SW2 */ 304 pmic_reg_read(p, REG_SW_1, &val); 305 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; 306 ret = pmic_reg_write(p, REG_SW_1, val); 307 if (ret) { 308 printf("Writing to REG_SW_1 failed: %d\n", ret); 309 return ret; 310 } 311 312 /* Set global reset timer to 4s */ 313 pmic_reg_read(p, REG_POWER_CTL2, &val); 314 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; 315 ret = pmic_reg_write(p, REG_POWER_CTL2, val); 316 if (ret) { 317 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); 318 return ret; 319 } 320 321 /* Set VUSBSEL and VUSBEN for USB PHY supply*/ 322 pmic_reg_read(p, REG_MODE_0, &val); 323 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); 324 ret = pmic_reg_write(p, REG_MODE_0, val); 325 if (ret) { 326 printf("Writing to REG_MODE_0 failed: %d\n", ret); 327 return ret; 328 } 329 330 /* Set SWBST to 5V in auto mode */ 331 val = SWBST_AUTO; 332 ret = pmic_reg_write(p, SWBST_CTRL, val); 333 if (ret) { 334 printf("Writing to SWBST_CTRL failed: %d\n", ret); 335 return ret; 336 } 337 338 return ret; 339 } 340 341 return -1; 342 } 343 344 static void clock_1GHz(void) 345 { 346 int ret; 347 u32 ref_clk = MXC_HCLK; 348 /* 349 * After increasing voltage to 1.25V, we can switch 350 * CPU clock to 1GHz and DDR to 400MHz safely 351 */ 352 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 353 if (ret) 354 printf("CPU: Switch CPU clock to 1GHZ failed\n"); 355 356 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 357 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 358 if (ret) 359 printf("CPU: Switch DDR clock to 400MHz failed\n"); 360 } 361 362 int board_early_init_f(void) 363 { 364 setup_iomux_uart(); 365 setup_iomux_fec(); 366 setup_iomux_lcd(); 367 368 return 0; 369 } 370 371 /* 372 * Do not overwrite the console 373 * Use always serial for U-Boot console 374 */ 375 int overwrite_console(void) 376 { 377 return 1; 378 } 379 380 int board_init(void) 381 { 382 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 383 384 mxc_set_sata_internal_clock(); 385 setup_iomux_i2c(); 386 387 return 0; 388 } 389 390 int board_late_init(void) 391 { 392 if (!power_init()) 393 clock_1GHz(); 394 395 return 0; 396 } 397 398 int checkboard(void) 399 { 400 puts("Board: MX53 LOCO\n"); 401 402 return 0; 403 } 404