1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * Jason Liu <r64343@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/iomux-mx53.h> 15 #include <asm/arch/clock.h> 16 #include <linux/errno.h> 17 #include <asm/mach-imx/mx5_video.h> 18 #include <netdev.h> 19 #include <i2c.h> 20 #include <input.h> 21 #include <mmc.h> 22 #include <fsl_esdhc.h> 23 #include <asm/gpio.h> 24 #include <power/pmic.h> 25 #include <dialog_pmic.h> 26 #include <fsl_pmic.h> 27 #include <linux/fb.h> 28 #include <ipu_pixfmt.h> 29 30 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 u32 get_board_rev(void) 35 { 36 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 37 struct fuse_bank *bank = &iim->bank[0]; 38 struct fuse_bank0_regs *fuse = 39 (struct fuse_bank0_regs *)bank->fuse_regs; 40 41 int rev = readl(&fuse->gp[6]); 42 43 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) 44 rev = 0; 45 46 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 47 } 48 49 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 50 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 51 52 static void setup_iomux_uart(void) 53 { 54 static const iomux_v3_cfg_t uart_pads[] = { 55 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), 56 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), 57 }; 58 59 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 60 } 61 62 #ifdef CONFIG_USB_EHCI_MX5 63 int board_ehci_hcd_init(int port) 64 { 65 /* request VBUS power enable pin, GPIO7_8 */ 66 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); 67 gpio_direction_output(IMX_GPIO_NR(7, 8), 1); 68 return 0; 69 } 70 #endif 71 72 static void setup_iomux_fec(void) 73 { 74 static const iomux_v3_cfg_t fec_pads[] = { 75 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 76 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), 77 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 78 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 79 PAD_CTL_HYS | PAD_CTL_PKE), 80 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 81 PAD_CTL_HYS | PAD_CTL_PKE), 82 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 83 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 84 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 85 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 86 PAD_CTL_HYS | PAD_CTL_PKE), 87 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 88 PAD_CTL_HYS | PAD_CTL_PKE), 89 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 90 PAD_CTL_HYS | PAD_CTL_PKE), 91 }; 92 93 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 94 } 95 96 #ifdef CONFIG_FSL_ESDHC 97 struct fsl_esdhc_cfg esdhc_cfg[2] = { 98 {MMC_SDHC1_BASE_ADDR}, 99 {MMC_SDHC3_BASE_ADDR}, 100 }; 101 102 int board_mmc_getcd(struct mmc *mmc) 103 { 104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 105 int ret; 106 107 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); 108 gpio_direction_input(IMX_GPIO_NR(3, 11)); 109 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); 110 gpio_direction_input(IMX_GPIO_NR(3, 13)); 111 112 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 113 ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); 114 else 115 ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); 116 117 return ret; 118 } 119 120 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 121 PAD_CTL_PUS_100K_UP) 122 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 123 PAD_CTL_DSE_HIGH) 124 125 int board_mmc_init(bd_t *bis) 126 { 127 static const iomux_v3_cfg_t sd1_pads[] = { 128 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 129 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 130 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 131 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 132 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 133 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 134 MX53_PAD_EIM_DA13__GPIO3_13, 135 }; 136 137 static const iomux_v3_cfg_t sd2_pads[] = { 138 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, 139 SD_CMD_PAD_CTRL), 140 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), 141 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), 142 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), 143 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), 144 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), 145 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), 146 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), 147 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), 148 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), 149 MX53_PAD_EIM_DA11__GPIO3_11, 150 }; 151 152 u32 index; 153 int ret; 154 155 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 156 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 157 158 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 159 switch (index) { 160 case 0: 161 imx_iomux_v3_setup_multiple_pads(sd1_pads, 162 ARRAY_SIZE(sd1_pads)); 163 break; 164 case 1: 165 imx_iomux_v3_setup_multiple_pads(sd2_pads, 166 ARRAY_SIZE(sd2_pads)); 167 break; 168 default: 169 printf("Warning: you configured more ESDHC controller" 170 "(%d) as supported by the board(2)\n", 171 CONFIG_SYS_FSL_ESDHC_NUM); 172 return -EINVAL; 173 } 174 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 175 if (ret) 176 return ret; 177 } 178 179 return 0; 180 } 181 #endif 182 183 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 184 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 185 186 static void setup_iomux_i2c(void) 187 { 188 static const iomux_v3_cfg_t i2c1_pads[] = { 189 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), 190 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), 191 }; 192 193 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); 194 } 195 196 static int power_init(void) 197 { 198 unsigned int val; 199 int ret; 200 struct pmic *p; 201 202 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { 203 ret = pmic_dialog_init(I2C_PMIC); 204 if (ret) 205 return ret; 206 207 p = pmic_get("DIALOG_PMIC"); 208 if (!p) 209 return -ENODEV; 210 211 env_set("fdt_file", "imx53-qsb.dtb"); 212 213 /* Set VDDA to 1.25V */ 214 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; 215 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); 216 if (ret) { 217 printf("Writing to BUCKCORE_REG failed: %d\n", ret); 218 return ret; 219 } 220 221 pmic_reg_read(p, DA9053_SUPPLY_REG, &val); 222 val |= DA9052_SUPPLY_VBCOREGO; 223 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); 224 if (ret) { 225 printf("Writing to SUPPLY_REG failed: %d\n", ret); 226 return ret; 227 } 228 229 /* Set Vcc peripheral to 1.30V */ 230 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); 231 if (ret) { 232 printf("Writing to BUCKPRO_REG failed: %d\n", ret); 233 return ret; 234 } 235 236 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); 237 if (ret) { 238 printf("Writing to SUPPLY_REG failed: %d\n", ret); 239 return ret; 240 } 241 242 return ret; 243 } 244 245 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { 246 ret = pmic_init(I2C_0); 247 if (ret) 248 return ret; 249 250 p = pmic_get("FSL_PMIC"); 251 if (!p) 252 return -ENODEV; 253 254 env_set("fdt_file", "imx53-qsrb.dtb"); 255 256 /* Set VDDGP to 1.25V for 1GHz on SW1 */ 257 pmic_reg_read(p, REG_SW_0, &val); 258 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; 259 ret = pmic_reg_write(p, REG_SW_0, val); 260 if (ret) { 261 printf("Writing to REG_SW_0 failed: %d\n", ret); 262 return ret; 263 } 264 265 /* Set VCC as 1.30V on SW2 */ 266 pmic_reg_read(p, REG_SW_1, &val); 267 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; 268 ret = pmic_reg_write(p, REG_SW_1, val); 269 if (ret) { 270 printf("Writing to REG_SW_1 failed: %d\n", ret); 271 return ret; 272 } 273 274 /* Set global reset timer to 4s */ 275 pmic_reg_read(p, REG_POWER_CTL2, &val); 276 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; 277 ret = pmic_reg_write(p, REG_POWER_CTL2, val); 278 if (ret) { 279 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); 280 return ret; 281 } 282 283 /* Set VUSBSEL and VUSBEN for USB PHY supply*/ 284 pmic_reg_read(p, REG_MODE_0, &val); 285 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); 286 ret = pmic_reg_write(p, REG_MODE_0, val); 287 if (ret) { 288 printf("Writing to REG_MODE_0 failed: %d\n", ret); 289 return ret; 290 } 291 292 /* Set SWBST to 5V in auto mode */ 293 val = SWBST_AUTO; 294 ret = pmic_reg_write(p, SWBST_CTRL, val); 295 if (ret) { 296 printf("Writing to SWBST_CTRL failed: %d\n", ret); 297 return ret; 298 } 299 300 return ret; 301 } 302 303 return -1; 304 } 305 306 static void clock_1GHz(void) 307 { 308 int ret; 309 u32 ref_clk = MXC_HCLK; 310 /* 311 * After increasing voltage to 1.25V, we can switch 312 * CPU clock to 1GHz and DDR to 400MHz safely 313 */ 314 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 315 if (ret) 316 printf("CPU: Switch CPU clock to 1GHZ failed\n"); 317 318 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 319 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 320 if (ret) 321 printf("CPU: Switch DDR clock to 400MHz failed\n"); 322 } 323 324 int board_early_init_f(void) 325 { 326 setup_iomux_uart(); 327 setup_iomux_fec(); 328 setup_iomux_lcd(); 329 330 return 0; 331 } 332 333 /* 334 * Do not overwrite the console 335 * Use always serial for U-Boot console 336 */ 337 int overwrite_console(void) 338 { 339 return 1; 340 } 341 342 int board_init(void) 343 { 344 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 345 346 mxc_set_sata_internal_clock(); 347 setup_iomux_i2c(); 348 349 return 0; 350 } 351 352 int board_late_init(void) 353 { 354 if (!power_init()) 355 clock_1GHz(); 356 357 return 0; 358 } 359 360 int checkboard(void) 361 { 362 puts("Board: MX53 LOCO\n"); 363 364 return 0; 365 } 366