1 /* 2 * (C) Copyright 2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/mx5x_pins.h> 27 #include <asm/arch/sys_proto.h> 28 #include <asm/arch/crm_regs.h> 29 #include <asm/arch/iomux.h> 30 #include <asm/errno.h> 31 #include <netdev.h> 32 #include <i2c.h> 33 #include <mmc.h> 34 #include <fsl_esdhc.h> 35 #include <pmic.h> 36 #include <fsl_pmic.h> 37 #include <asm/gpio.h> 38 #include <mc13892.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 u32 get_board_rev(void) 43 { 44 return get_cpu_rev(); 45 } 46 47 int dram_init(void) 48 { 49 /* dram_init must store complete ramsize in gd->ram_size */ 50 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 51 PHYS_SDRAM_1_SIZE); 52 return 0; 53 } 54 55 static void setup_iomux_uart(void) 56 { 57 /* UART1 RXD */ 58 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); 59 mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 60 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 61 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 62 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 63 PAD_CTL_ODE_OPENDRAIN_ENABLE); 64 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); 65 66 /* UART1 TXD */ 67 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); 68 mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 69 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 70 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 71 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 72 PAD_CTL_ODE_OPENDRAIN_ENABLE); 73 } 74 75 static void setup_i2c(unsigned int port_number) 76 { 77 switch (port_number) { 78 case 0: 79 /* i2c1 SDA */ 80 mxc_request_iomux(MX53_PIN_CSI0_D8, 81 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); 82 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, 83 INPUT_CTL_PATH0); 84 mxc_iomux_set_pad(MX53_PIN_CSI0_D8, 85 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 86 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | 87 PAD_CTL_ODE_OPENDRAIN_ENABLE); 88 /* i2c1 SCL */ 89 mxc_request_iomux(MX53_PIN_CSI0_D9, 90 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); 91 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, 92 INPUT_CTL_PATH0); 93 mxc_iomux_set_pad(MX53_PIN_CSI0_D9, 94 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 95 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | 96 PAD_CTL_ODE_OPENDRAIN_ENABLE); 97 break; 98 case 1: 99 /* i2c2 SDA */ 100 mxc_request_iomux(MX53_PIN_KEY_ROW3, 101 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); 102 mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, 103 INPUT_CTL_PATH0); 104 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, 105 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 106 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | 107 PAD_CTL_ODE_OPENDRAIN_ENABLE); 108 109 /* i2c2 SCL */ 110 mxc_request_iomux(MX53_PIN_KEY_COL3, 111 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); 112 mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, 113 INPUT_CTL_PATH0); 114 mxc_iomux_set_pad(MX53_PIN_KEY_COL3, 115 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | 116 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | 117 PAD_CTL_ODE_OPENDRAIN_ENABLE); 118 break; 119 default: 120 printf("Warning: Wrong I2C port number\n"); 121 break; 122 } 123 } 124 125 void power_init(void) 126 { 127 unsigned int val; 128 struct pmic *p; 129 130 pmic_init(); 131 p = get_pmic(); 132 133 /* Set VDDA to 1.25V */ 134 pmic_reg_read(p, REG_SW_2, &val); 135 val &= ~SWX_OUT_MASK; 136 val |= SWX_OUT_1_25; 137 pmic_reg_write(p, REG_SW_2, val); 138 139 /* 140 * Need increase VCC and VDDA to 1.3V 141 * according to MX53 IC TO2 datasheet. 142 */ 143 if (is_soc_rev(CHIP_REV_2_0) == 0) { 144 /* Set VCC to 1.3V for TO2 */ 145 pmic_reg_read(p, REG_SW_1, &val); 146 val &= ~SWX_OUT_MASK; 147 val |= SWX_OUT_1_30; 148 pmic_reg_write(p, REG_SW_1, val); 149 150 /* Set VDDA to 1.3V for TO2 */ 151 pmic_reg_read(p, REG_SW_2, &val); 152 val &= ~SWX_OUT_MASK; 153 val |= SWX_OUT_1_30; 154 pmic_reg_write(p, REG_SW_2, val); 155 } 156 } 157 158 static void setup_iomux_fec(void) 159 { 160 /*FEC_MDIO*/ 161 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); 162 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 163 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 164 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 165 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); 166 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); 167 168 /*FEC_MDC*/ 169 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); 170 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); 171 172 /* FEC RXD1 */ 173 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); 174 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 175 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 176 177 /* FEC RXD0 */ 178 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); 179 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 180 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 181 182 /* FEC TXD1 */ 183 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); 184 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); 185 186 /* FEC TXD0 */ 187 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); 188 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); 189 190 /* FEC TX_EN */ 191 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); 192 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); 193 194 /* FEC TX_CLK */ 195 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); 196 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 197 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 198 199 /* FEC RX_ER */ 200 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); 201 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 202 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 203 204 /* FEC CRS */ 205 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); 206 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 207 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); 208 } 209 210 #ifdef CONFIG_FSL_ESDHC 211 struct fsl_esdhc_cfg esdhc_cfg[2] = { 212 {MMC_SDHC1_BASE_ADDR, 1}, 213 {MMC_SDHC3_BASE_ADDR, 1}, 214 }; 215 216 int board_mmc_getcd(u8 *cd, struct mmc *mmc) 217 { 218 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 219 220 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 221 *cd = gpio_get_value(77); /*GPIO3_13*/ 222 else 223 *cd = gpio_get_value(75); /*GPIO3_11*/ 224 225 return 0; 226 } 227 228 int board_mmc_init(bd_t *bis) 229 { 230 u32 index; 231 s32 status = 0; 232 233 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 234 switch (index) { 235 case 0: 236 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); 237 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); 238 mxc_request_iomux(MX53_PIN_SD1_DATA0, 239 IOMUX_CONFIG_ALT0); 240 mxc_request_iomux(MX53_PIN_SD1_DATA1, 241 IOMUX_CONFIG_ALT0); 242 mxc_request_iomux(MX53_PIN_SD1_DATA2, 243 IOMUX_CONFIG_ALT0); 244 mxc_request_iomux(MX53_PIN_SD1_DATA3, 245 IOMUX_CONFIG_ALT0); 246 mxc_request_iomux(MX53_PIN_EIM_DA13, 247 IOMUX_CONFIG_ALT1); 248 249 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 250 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 251 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 252 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 253 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 254 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 255 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 256 PAD_CTL_DRV_HIGH); 257 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 258 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 259 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 260 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 261 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 262 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 263 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 264 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 265 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 266 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 267 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 268 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 269 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 270 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 271 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 272 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 273 break; 274 case 1: 275 mxc_request_iomux(MX53_PIN_ATA_RESET_B, 276 IOMUX_CONFIG_ALT2); 277 mxc_request_iomux(MX53_PIN_ATA_IORDY, 278 IOMUX_CONFIG_ALT2); 279 mxc_request_iomux(MX53_PIN_ATA_DATA8, 280 IOMUX_CONFIG_ALT4); 281 mxc_request_iomux(MX53_PIN_ATA_DATA9, 282 IOMUX_CONFIG_ALT4); 283 mxc_request_iomux(MX53_PIN_ATA_DATA10, 284 IOMUX_CONFIG_ALT4); 285 mxc_request_iomux(MX53_PIN_ATA_DATA11, 286 IOMUX_CONFIG_ALT4); 287 mxc_request_iomux(MX53_PIN_ATA_DATA0, 288 IOMUX_CONFIG_ALT4); 289 mxc_request_iomux(MX53_PIN_ATA_DATA1, 290 IOMUX_CONFIG_ALT4); 291 mxc_request_iomux(MX53_PIN_ATA_DATA2, 292 IOMUX_CONFIG_ALT4); 293 mxc_request_iomux(MX53_PIN_ATA_DATA3, 294 IOMUX_CONFIG_ALT4); 295 mxc_request_iomux(MX53_PIN_EIM_DA11, 296 IOMUX_CONFIG_ALT1); 297 298 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 299 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 300 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 301 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); 302 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 303 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 304 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 305 PAD_CTL_DRV_HIGH); 306 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 307 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 308 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 309 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 310 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 311 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 312 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 313 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 314 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 315 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 316 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 317 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 318 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 319 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 320 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 321 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 322 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 323 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 324 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 325 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 326 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 327 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 328 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 329 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 330 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 331 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 332 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 333 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 334 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 335 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 336 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 337 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); 338 339 break; 340 default: 341 printf("Warning: you configured more ESDHC controller" 342 "(%d) as supported by the board(2)\n", 343 CONFIG_SYS_FSL_ESDHC_NUM); 344 return status; 345 } 346 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 347 } 348 349 return status; 350 } 351 #endif 352 353 int board_early_init_f(void) 354 { 355 setup_iomux_uart(); 356 setup_iomux_fec(); 357 358 return 0; 359 } 360 361 int board_init(void) 362 { 363 /* address of boot parameters */ 364 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 365 366 return 0; 367 } 368 369 int board_late_init(void) 370 { 371 setup_i2c(1); 372 power_init(); 373 374 return 0; 375 } 376 377 int checkboard(void) 378 { 379 puts("Board: MX53EVK\n"); 380 381 return 0; 382 } 383