1 /* 2 * (C) Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/mx5x_pins.h> 27 #include <asm/arch/sys_proto.h> 28 #include <asm/arch/crm_regs.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch/iomux.h> 31 #include <asm/errno.h> 32 #include <netdev.h> 33 #include <mmc.h> 34 #include <fsl_esdhc.h> 35 #include <asm/gpio.h> 36 37 #define ETHERNET_INT IMX_GPIO_NR(2, 31) 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 int dram_init(void) 42 { 43 u32 size1, size2; 44 45 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 46 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 47 48 gd->ram_size = size1 + size2; 49 50 return 0; 51 } 52 void dram_init_banksize(void) 53 { 54 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 55 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 56 57 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 58 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 59 } 60 61 static void setup_iomux_uart(void) 62 { 63 /* UART1 RXD */ 64 mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); 65 mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, 66 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 67 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 68 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 69 PAD_CTL_ODE_OPENDRAIN_ENABLE); 70 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); 71 72 /* UART1 TXD */ 73 mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); 74 mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, 75 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | 76 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | 77 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | 78 PAD_CTL_ODE_OPENDRAIN_ENABLE); 79 } 80 81 #ifdef CONFIG_FSL_ESDHC 82 struct fsl_esdhc_cfg esdhc_cfg[2] = { 83 {MMC_SDHC1_BASE_ADDR}, 84 {MMC_SDHC2_BASE_ADDR}, 85 }; 86 87 int board_mmc_getcd(struct mmc *mmc) 88 { 89 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 90 int ret; 91 92 mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); 93 gpio_direction_input(IMX_GPIO_NR(1, 1)); 94 mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); 95 gpio_direction_input(IMX_GPIO_NR(1, 4)); 96 97 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 98 ret = !gpio_get_value(IMX_GPIO_NR(1, 1)); 99 else 100 ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); 101 102 return ret; 103 } 104 105 int board_mmc_init(bd_t *bis) 106 { 107 u32 index; 108 s32 status = 0; 109 110 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 111 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 112 113 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 114 switch (index) { 115 case 0: 116 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); 117 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); 118 mxc_request_iomux(MX53_PIN_SD1_DATA0, 119 IOMUX_CONFIG_ALT0); 120 mxc_request_iomux(MX53_PIN_SD1_DATA1, 121 IOMUX_CONFIG_ALT0); 122 mxc_request_iomux(MX53_PIN_SD1_DATA2, 123 IOMUX_CONFIG_ALT0); 124 mxc_request_iomux(MX53_PIN_SD1_DATA3, 125 IOMUX_CONFIG_ALT0); 126 127 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); 128 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); 129 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); 130 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); 131 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); 132 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); 133 break; 134 case 1: 135 mxc_request_iomux(MX53_PIN_SD2_CMD, 136 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 137 mxc_request_iomux(MX53_PIN_SD2_CLK, 138 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 139 mxc_request_iomux(MX53_PIN_SD2_DATA0, 140 IOMUX_CONFIG_ALT0); 141 mxc_request_iomux(MX53_PIN_SD2_DATA1, 142 IOMUX_CONFIG_ALT0); 143 mxc_request_iomux(MX53_PIN_SD2_DATA2, 144 IOMUX_CONFIG_ALT0); 145 mxc_request_iomux(MX53_PIN_SD2_DATA3, 146 IOMUX_CONFIG_ALT0); 147 mxc_request_iomux(MX53_PIN_ATA_DATA12, 148 IOMUX_CONFIG_ALT2); 149 mxc_request_iomux(MX53_PIN_ATA_DATA13, 150 IOMUX_CONFIG_ALT2); 151 mxc_request_iomux(MX53_PIN_ATA_DATA14, 152 IOMUX_CONFIG_ALT2); 153 mxc_request_iomux(MX53_PIN_ATA_DATA15, 154 IOMUX_CONFIG_ALT2); 155 156 mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4); 157 mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4); 158 mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4); 159 mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4); 160 mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4); 161 mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4); 162 mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4); 163 mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4); 164 mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4); 165 mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4); 166 break; 167 default: 168 printf("Warning: you configured more ESDHC controller" 169 "(%d) as supported by the board(2)\n", 170 CONFIG_SYS_FSL_ESDHC_NUM); 171 return status; 172 } 173 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 174 } 175 176 return status; 177 } 178 #endif 179 180 static void weim_smc911x_iomux(void) 181 { 182 /* ETHERNET_INT as GPIO2_31 */ 183 mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); 184 gpio_direction_input(ETHERNET_INT); 185 186 /* Data bus */ 187 mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0); 188 mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4); 189 190 mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0); 191 mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4); 192 193 mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0); 194 mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4); 195 196 mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0); 197 mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4); 198 199 mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0); 200 mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4); 201 202 mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0); 203 mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4); 204 205 mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0); 206 mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4); 207 208 mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0); 209 mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4); 210 211 mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0); 212 mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4); 213 214 mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0); 215 mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4); 216 217 mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0); 218 mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4); 219 220 mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0); 221 mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4); 222 223 mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0); 224 mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4); 225 226 mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0); 227 mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4); 228 229 mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0); 230 mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4); 231 232 mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0); 233 mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4); 234 235 /* Address lines */ 236 mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); 237 mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4); 238 239 mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); 240 mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4); 241 242 mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); 243 mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4); 244 245 mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); 246 mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4); 247 248 mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); 249 mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4); 250 251 mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); 252 mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4); 253 254 mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); 255 mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4); 256 257 /* other EIM signals for ethernet */ 258 mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0); 259 mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0); 260 mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0); 261 } 262 263 static void weim_cs1_settings(void) 264 { 265 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; 266 267 writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1); 268 writel(0x0, &weim_regs->cs1gcr2); 269 writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1); 270 writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2); 271 writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1); 272 writel(0x0, &weim_regs->cs1wcr2); 273 writel(0x0, &weim_regs->wcr); 274 275 set_chipselect_size(CS0_64M_CS1_64M); 276 } 277 278 int board_early_init_f(void) 279 { 280 setup_iomux_uart(); 281 return 0; 282 } 283 284 int board_init(void) 285 { 286 /* address of boot parameters */ 287 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 288 289 return 0; 290 } 291 292 int board_eth_init(bd_t *bis) 293 { 294 int rc = -ENODEV; 295 296 weim_smc911x_iomux(); 297 weim_cs1_settings(); 298 299 #ifdef CONFIG_SMC911X 300 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 301 #endif 302 return rc; 303 } 304 305 int checkboard(void) 306 { 307 puts("Board: MX53ARD\n"); 308 309 return 0; 310 } 311