1 /*
2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx5x_pins.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/iomux.h>
30 #include <asm/errno.h>
31 #include <netdev.h>
32 #include <mmc.h>
33 #include <fsl_esdhc.h>
34 #include <asm/gpio.h>
35 
36 #define ETHERNET_INT		(1 * 32 + 31)  /* GPIO2_31 */
37 
38 DECLARE_GLOBAL_DATA_PTR;
39 
40 int dram_init(void)
41 {
42 	u32 size1, size2;
43 
44 	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
45 	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
46 
47 	gd->ram_size = size1 + size2;
48 
49 	return 0;
50 }
51 void dram_init_banksize(void)
52 {
53 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
54 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
55 
56 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
57 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
58 }
59 
60 static void setup_iomux_uart(void)
61 {
62 	/* UART1 RXD */
63 	mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
64 	mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
65 				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
66 				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
67 				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
68 				PAD_CTL_ODE_OPENDRAIN_ENABLE);
69 	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
70 
71 	/* UART1 TXD */
72 	mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
73 	mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
74 				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
75 				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
76 				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
77 				PAD_CTL_ODE_OPENDRAIN_ENABLE);
78 }
79 
80 #ifdef CONFIG_FSL_ESDHC
81 struct fsl_esdhc_cfg esdhc_cfg[2] = {
82 	{MMC_SDHC1_BASE_ADDR, 1 },
83 	{MMC_SDHC2_BASE_ADDR, 1 },
84 };
85 
86 int board_mmc_getcd(struct mmc *mmc)
87 {
88 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
89 	int ret;
90 
91 	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
92 	gpio_direction_input(1);
93 	mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
94 	gpio_direction_input(4);
95 
96 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
97 		ret = !gpio_get_value(1); /* GPIO1_1 */
98 	else
99 		ret = !gpio_get_value(4); /* GPIO1_4 */
100 
101 	return ret;
102 }
103 
104 int board_mmc_init(bd_t *bis)
105 {
106 	u32 index;
107 	s32 status = 0;
108 
109 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
110 		switch (index) {
111 		case 0:
112 			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
113 			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
114 			mxc_request_iomux(MX53_PIN_SD1_DATA0,
115 						IOMUX_CONFIG_ALT0);
116 			mxc_request_iomux(MX53_PIN_SD1_DATA1,
117 						IOMUX_CONFIG_ALT0);
118 			mxc_request_iomux(MX53_PIN_SD1_DATA2,
119 						IOMUX_CONFIG_ALT0);
120 			mxc_request_iomux(MX53_PIN_SD1_DATA3,
121 						IOMUX_CONFIG_ALT0);
122 
123 			mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
124 			mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
125 			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
126 			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
127 			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
128 			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
129 			break;
130 		case 1:
131 			mxc_request_iomux(MX53_PIN_SD2_CMD,
132 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
133 			mxc_request_iomux(MX53_PIN_SD2_CLK,
134 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
135 			mxc_request_iomux(MX53_PIN_SD2_DATA0,
136 						IOMUX_CONFIG_ALT0);
137 			mxc_request_iomux(MX53_PIN_SD2_DATA1,
138 						IOMUX_CONFIG_ALT0);
139 			mxc_request_iomux(MX53_PIN_SD2_DATA2,
140 						IOMUX_CONFIG_ALT0);
141 			mxc_request_iomux(MX53_PIN_SD2_DATA3,
142 						IOMUX_CONFIG_ALT0);
143 			mxc_request_iomux(MX53_PIN_ATA_DATA12,
144 						IOMUX_CONFIG_ALT2);
145 			mxc_request_iomux(MX53_PIN_ATA_DATA13,
146 						IOMUX_CONFIG_ALT2);
147 			mxc_request_iomux(MX53_PIN_ATA_DATA14,
148 						IOMUX_CONFIG_ALT2);
149 			mxc_request_iomux(MX53_PIN_ATA_DATA15,
150 						IOMUX_CONFIG_ALT2);
151 
152 			mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
153 			mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
154 			mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
155 			mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
156 			mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
157 			mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
158 			mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
159 			mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
160 			mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
161 			mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
162 			break;
163 		default:
164 			printf("Warning: you configured more ESDHC controller"
165 				"(%d) as supported by the board(2)\n",
166 				CONFIG_SYS_FSL_ESDHC_NUM);
167 			return status;
168 		}
169 		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
170 	}
171 
172 	return status;
173 }
174 #endif
175 
176 static void weim_smc911x_iomux(void)
177 {
178 	/* ETHERNET_INT as GPIO2_31 */
179 	mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
180 	gpio_direction_input(ETHERNET_INT);
181 
182 	/* Data bus */
183 	mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
184 	mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
185 
186 	mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
187 	mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
188 
189 	mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
190 	mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
191 
192 	mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
193 	mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
194 
195 	mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
196 	mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
197 
198 	mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
199 	mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
200 
201 	mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
202 	mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
203 
204 	mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
205 	mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
206 
207 	mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
208 	mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
209 
210 	mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
211 	mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
212 
213 	mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
214 	mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
215 
216 	mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
217 	mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
218 
219 	mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
220 	mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
221 
222 	mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
223 	mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
224 
225 	mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
226 	mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
227 
228 	mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
229 	mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
230 
231 	/* Address lines */
232 	mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
233 	mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
234 
235 	mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
236 	mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
237 
238 	mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
239 	mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
240 
241 	mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
242 	mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
243 
244 	mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
245 	mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
246 
247 	mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
248 	mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
249 
250 	mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
251 	mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
252 
253 	/* other EIM signals for ethernet */
254 	mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
255 	mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
256 	mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
257 }
258 
259 static void weim_cs1_settings(void)
260 {
261 	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
262 
263 	writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
264 	writel(0x0, &weim_regs->cs1gcr2);
265 	writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
266 	writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
267 	writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
268 	writel(0x0, &weim_regs->cs1wcr2);
269 	writel(0x0, &weim_regs->wcr);
270 
271 	set_chipselect_size(CS0_64M_CS1_64M);
272 }
273 
274 int board_early_init_f(void)
275 {
276 	setup_iomux_uart();
277 	return 0;
278 }
279 
280 int board_init(void)
281 {
282 	/* address of boot parameters */
283 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
284 
285 	return 0;
286 }
287 
288 int board_eth_init(bd_t *bis)
289 {
290 	int rc = 0;
291 
292 	weim_smc911x_iomux();
293 	weim_cs1_settings();
294 
295 #ifdef CONFIG_SMC911X
296 	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
297 #endif
298 	return rc;
299 }
300 
301 int checkboard(void)
302 {
303 	puts("Board: MX53ARD\n");
304 
305 	return 0;
306 }
307