1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/gpio.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux-mx51.h>
12 #include <asm/errno.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/imx-common/mx5_video.h>
17 #include <i2c.h>
18 #include <mmc.h>
19 #include <fsl_esdhc.h>
20 #include <power/pmic.h>
21 #include <fsl_pmic.h>
22 #include <mc13892.h>
23 #include <usb/ehci-fsl.h>
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 #ifdef CONFIG_FSL_ESDHC
28 struct fsl_esdhc_cfg esdhc_cfg[2] = {
29 	{MMC_SDHC1_BASE_ADDR},
30 	{MMC_SDHC2_BASE_ADDR},
31 };
32 #endif
33 
34 int dram_init(void)
35 {
36 	/* dram_init must store complete ramsize in gd->ram_size */
37 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
38 				PHYS_SDRAM_1_SIZE);
39 	return 0;
40 }
41 
42 u32 get_board_rev(void)
43 {
44 	u32 rev = get_cpu_rev();
45 	if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
46 		rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
47 	return rev;
48 }
49 
50 #define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
51 
52 static void setup_iomux_uart(void)
53 {
54 	static const iomux_v3_cfg_t uart_pads[] = {
55 		MX51_PAD_UART1_RXD__UART1_RXD,
56 		MX51_PAD_UART1_TXD__UART1_TXD,
57 		NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
58 		NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
59 	};
60 
61 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
62 }
63 
64 static void setup_iomux_fec(void)
65 {
66 	static const iomux_v3_cfg_t fec_pads[] = {
67 		NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
68 				PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
69 				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
70 		MX51_PAD_NANDF_CS3__FEC_MDC,
71 		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
72 		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
73 		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
74 		MX51_PAD_NANDF_D9__FEC_RDATA0,
75 		MX51_PAD_NANDF_CS6__FEC_TDATA3,
76 		MX51_PAD_NANDF_CS5__FEC_TDATA2,
77 		MX51_PAD_NANDF_CS4__FEC_TDATA1,
78 		MX51_PAD_NANDF_D8__FEC_TDATA0,
79 		MX51_PAD_NANDF_CS7__FEC_TX_EN,
80 		MX51_PAD_NANDF_CS2__FEC_TX_ER,
81 		MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
82 		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
83 		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
84 		MX51_PAD_EIM_CS5__FEC_CRS,
85 		MX51_PAD_EIM_CS4__FEC_RX_ER,
86 		NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
87 	};
88 
89 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
90 }
91 
92 #ifdef CONFIG_MXC_SPI
93 static void setup_iomux_spi(void)
94 {
95 	static const iomux_v3_cfg_t spi_pads[] = {
96 		NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
97 				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
98 		NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
99 				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
100 		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
101 				MX51_GPIO_PAD_CTRL),
102 		MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
103 		NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
104 		NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
105 				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
106 	};
107 
108 	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
109 }
110 #endif
111 
112 #ifdef CONFIG_USB_EHCI_MX5
113 #define MX51EVK_USBH1_HUB_RST	IMX_GPIO_NR(1, 7)
114 #define MX51EVK_USBH1_STP	IMX_GPIO_NR(1, 27)
115 #define MX51EVK_USB_CLK_EN_B	IMX_GPIO_NR(2, 2)
116 #define MX51EVK_USB_PHY_RESET	IMX_GPIO_NR(2, 5)
117 
118 static void setup_usb_h1(void)
119 {
120 	static const iomux_v3_cfg_t usb_h1_pads[] = {
121 		MX51_PAD_USBH1_CLK__USBH1_CLK,
122 		MX51_PAD_USBH1_DIR__USBH1_DIR,
123 		MX51_PAD_USBH1_STP__USBH1_STP,
124 		MX51_PAD_USBH1_NXT__USBH1_NXT,
125 		MX51_PAD_USBH1_DATA0__USBH1_DATA0,
126 		MX51_PAD_USBH1_DATA1__USBH1_DATA1,
127 		MX51_PAD_USBH1_DATA2__USBH1_DATA2,
128 		MX51_PAD_USBH1_DATA3__USBH1_DATA3,
129 		MX51_PAD_USBH1_DATA4__USBH1_DATA4,
130 		MX51_PAD_USBH1_DATA5__USBH1_DATA5,
131 		MX51_PAD_USBH1_DATA6__USBH1_DATA6,
132 		MX51_PAD_USBH1_DATA7__USBH1_DATA7,
133 
134 		NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
135 		MX51_PAD_EIM_D17__GPIO2_1,
136 		MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
137 	};
138 
139 	imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
140 }
141 
142 int board_ehci_hcd_init(int port)
143 {
144 	/* Set USBH1_STP to GPIO and toggle it */
145 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
146 						MX51_USBH_PAD_CTRL));
147 
148 	gpio_direction_output(MX51EVK_USBH1_STP, 0);
149 	gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
150 	mdelay(10);
151 	gpio_set_value(MX51EVK_USBH1_STP, 1);
152 
153 	/* Set back USBH1_STP to be function */
154 	imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
155 
156 	/* De-assert USB PHY RESETB */
157 	gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
158 
159 	/* Drive USB_CLK_EN_B line low */
160 	gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
161 
162 	/* Reset USB hub */
163 	gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
164 	mdelay(2);
165 	gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
166 	return 0;
167 }
168 #endif
169 
170 static void power_init(void)
171 {
172 	unsigned int val;
173 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
174 	struct pmic *p;
175 	int ret;
176 
177 	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
178 	if (ret)
179 		return;
180 
181 	p = pmic_get("FSL_PMIC");
182 	if (!p)
183 		return;
184 
185 	/* Write needed to Power Gate 2 register */
186 	pmic_reg_read(p, REG_POWER_MISC, &val);
187 	val &= ~PWGT2SPIEN;
188 	pmic_reg_write(p, REG_POWER_MISC, val);
189 
190 	/* Externally powered */
191 	pmic_reg_read(p, REG_CHARGE, &val);
192 	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
193 	pmic_reg_write(p, REG_CHARGE, val);
194 
195 	/* power up the system first */
196 	pmic_reg_write(p, REG_POWER_MISC, PWUP);
197 
198 	/* Set core voltage to 1.1V */
199 	pmic_reg_read(p, REG_SW_0, &val);
200 	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
201 	pmic_reg_write(p, REG_SW_0, val);
202 
203 	/* Setup VCC (SW2) to 1.25 */
204 	pmic_reg_read(p, REG_SW_1, &val);
205 	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
206 	pmic_reg_write(p, REG_SW_1, val);
207 
208 	/* Setup 1V2_DIG1 (SW3) to 1.25 */
209 	pmic_reg_read(p, REG_SW_2, &val);
210 	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
211 	pmic_reg_write(p, REG_SW_2, val);
212 	udelay(50);
213 
214 	/* Raise the core frequency to 800MHz */
215 	writel(0x0, &mxc_ccm->cacrr);
216 
217 	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
218 	/* Setup the switcher mode for SW1 & SW2*/
219 	pmic_reg_read(p, REG_SW_4, &val);
220 	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
221 		(SWMODE_MASK << SWMODE2_SHIFT)));
222 	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
223 		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
224 	pmic_reg_write(p, REG_SW_4, val);
225 
226 	/* Setup the switcher mode for SW3 & SW4 */
227 	pmic_reg_read(p, REG_SW_5, &val);
228 	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
229 		(SWMODE_MASK << SWMODE4_SHIFT)));
230 	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
231 		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
232 	pmic_reg_write(p, REG_SW_5, val);
233 
234 	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
235 	pmic_reg_read(p, REG_SETTING_0, &val);
236 	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
237 	val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
238 	pmic_reg_write(p, REG_SETTING_0, val);
239 
240 	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
241 	pmic_reg_read(p, REG_SETTING_1, &val);
242 	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
243 	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
244 	pmic_reg_write(p, REG_SETTING_1, val);
245 
246 	/* Configure VGEN3 and VCAM regulators to use external PNP */
247 	val = VGEN3CONFIG | VCAMCONFIG;
248 	pmic_reg_write(p, REG_MODE_1, val);
249 	udelay(200);
250 
251 	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
252 	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
253 		VVIDEOEN | VAUDIOEN  | VSDEN;
254 	pmic_reg_write(p, REG_MODE_1, val);
255 
256 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
257 						NO_PAD_CTRL));
258 	gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
259 
260 	udelay(500);
261 
262 	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
263 }
264 
265 #ifdef CONFIG_FSL_ESDHC
266 int board_mmc_getcd(struct mmc *mmc)
267 {
268 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
269 	int ret;
270 
271 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
272 						NO_PAD_CTRL));
273 	gpio_direction_input(IMX_GPIO_NR(1, 0));
274 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
275 						NO_PAD_CTRL));
276 	gpio_direction_input(IMX_GPIO_NR(1, 6));
277 
278 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
279 		ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
280 	else
281 		ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
282 
283 	return ret;
284 }
285 
286 int board_mmc_init(bd_t *bis)
287 {
288 	static const iomux_v3_cfg_t sd1_pads[] = {
289 		NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
290 			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
291 		NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
292 			PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
293 		NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
294 			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
295 		NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
296 			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
297 		NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
298 			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
299 		NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
300 			PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
301 		NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
302 		NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
303 	};
304 
305 	static const iomux_v3_cfg_t sd2_pads[] = {
306 		NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
307 				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
308 		NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
309 				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
310 		NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
311 				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
312 		NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
313 				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
314 		NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
315 				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
316 		NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
317 				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
318 		NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
319 		NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
320 	};
321 
322 	u32 index;
323 	s32 status = 0;
324 
325 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
326 	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
327 
328 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
329 			index++) {
330 		switch (index) {
331 		case 0:
332 			imx_iomux_v3_setup_multiple_pads(sd1_pads,
333 							 ARRAY_SIZE(sd1_pads));
334 			break;
335 		case 1:
336 			imx_iomux_v3_setup_multiple_pads(sd2_pads,
337 							 ARRAY_SIZE(sd2_pads));
338 			break;
339 		default:
340 			printf("Warning: you configured more ESDHC controller"
341 				"(%d) as supported by the board(2)\n",
342 				CONFIG_SYS_FSL_ESDHC_NUM);
343 			return status;
344 		}
345 		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
346 	}
347 	return status;
348 }
349 #endif
350 
351 int board_early_init_f(void)
352 {
353 	setup_iomux_uart();
354 	setup_iomux_fec();
355 #ifdef CONFIG_USB_EHCI_MX5
356 	setup_usb_h1();
357 #endif
358 	setup_iomux_lcd();
359 
360 	return 0;
361 }
362 
363 int board_init(void)
364 {
365 	/* address of boot parameters */
366 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
367 
368 	return 0;
369 }
370 
371 #ifdef CONFIG_BOARD_LATE_INIT
372 int board_late_init(void)
373 {
374 #ifdef CONFIG_MXC_SPI
375 	setup_iomux_spi();
376 	power_init();
377 #endif
378 
379 	return 0;
380 }
381 #endif
382 
383 /*
384  * Do not overwrite the console
385  * Use always serial for U-Boot console
386  */
387 int overwrite_console(void)
388 {
389 	return 1;
390 }
391 
392 int checkboard(void)
393 {
394 	puts("Board: MX51EVK\n");
395 
396 	return 0;
397 }
398