1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/gpio.h> 26 #include <asm/arch/imx-regs.h> 27 #include <asm/arch/mx5x_pins.h> 28 #include <asm/arch/iomux.h> 29 #include <asm/errno.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/arch/crm_regs.h> 32 #include <i2c.h> 33 #include <mmc.h> 34 #include <fsl_esdhc.h> 35 #include <pmic.h> 36 #include <fsl_pmic.h> 37 #include <mc13892.h> 38 #include <usb/ehci-fsl.h> 39 #include <linux/fb.h> 40 #include <ipu_pixfmt.h> 41 42 #define MX51EVK_LCD_3V3 (3 * 32 + 9) /* GPIO4_9 */ 43 #define MX51EVK_LCD_5V (3 * 32 + 10) /* GPIO4_10 */ 44 #define MX51EVK_LCD_BACKLIGHT (2 * 32 + 4) /* GPIO3_4 */ 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 #ifdef CONFIG_FSL_ESDHC 49 struct fsl_esdhc_cfg esdhc_cfg[2] = { 50 {MMC_SDHC1_BASE_ADDR, 1}, 51 {MMC_SDHC2_BASE_ADDR, 1}, 52 }; 53 #endif 54 55 int dram_init(void) 56 { 57 /* dram_init must store complete ramsize in gd->ram_size */ 58 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 59 PHYS_SDRAM_1_SIZE); 60 return 0; 61 } 62 63 static void setup_iomux_uart(void) 64 { 65 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | 66 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; 67 68 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); 69 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); 70 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); 71 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); 72 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); 73 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); 74 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); 75 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); 76 } 77 78 static void setup_iomux_fec(void) 79 { 80 /*FEC_MDIO*/ 81 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3); 82 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD); 83 84 /*FEC_MDC*/ 85 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); 86 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); 87 88 /* FEC RDATA[3] */ 89 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); 90 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); 91 92 /* FEC RDATA[2] */ 93 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); 94 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); 95 96 /* FEC RDATA[1] */ 97 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); 98 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); 99 100 /* FEC RDATA[0] */ 101 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); 102 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); 103 104 /* FEC TDATA[3] */ 105 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); 106 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); 107 108 /* FEC TDATA[2] */ 109 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); 110 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); 111 112 /* FEC TDATA[1] */ 113 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); 114 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); 115 116 /* FEC TDATA[0] */ 117 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); 118 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); 119 120 /* FEC TX_EN */ 121 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); 122 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); 123 124 /* FEC TX_ER */ 125 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); 126 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); 127 128 /* FEC TX_CLK */ 129 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); 130 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); 131 132 /* FEC TX_COL */ 133 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); 134 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); 135 136 /* FEC RX_CLK */ 137 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); 138 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); 139 140 /* FEC RX_CRS */ 141 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); 142 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); 143 144 /* FEC RX_ER */ 145 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); 146 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); 147 148 /* FEC RX_DV */ 149 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); 150 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); 151 } 152 153 #ifdef CONFIG_MXC_SPI 154 static void setup_iomux_spi(void) 155 { 156 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ 157 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); 158 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105); 159 160 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ 161 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); 162 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105); 163 164 /* de-select SS1 of instance: ecspi1. */ 165 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); 166 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85); 167 168 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */ 169 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); 170 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185); 171 172 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */ 173 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); 174 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180); 175 176 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ 177 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); 178 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105); 179 } 180 #endif 181 182 #ifdef CONFIG_USB_EHCI_MX5 183 #define MX51EVK_USBH1_HUB_RST IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */ 184 #define MX51EVK_USBH1_STP IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */ 185 #define MX51EVK_USB_CLK_EN_B IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */ 186 #define MX51EVK_USB_PHY_RESET IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */ 187 188 #define USBH1_PAD (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \ 189 PAD_CTL_100K_PU | PAD_CTL_PUE_PULL | \ 190 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE) 191 #define GPIO_PAD (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | \ 192 PAD_CTL_SRE_FAST) 193 #define NO_PAD (1 << 16) 194 195 static void setup_usb_h1(void) 196 { 197 setup_iomux_usb_h1(); 198 199 /* GPIO_1_7 for USBH1 hub reset */ 200 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0); 201 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD); 202 203 /* GPIO_2_1 */ 204 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1); 205 mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD); 206 207 /* GPIO_2_5 for USB PHY reset */ 208 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1); 209 mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD); 210 } 211 212 int board_ehci_hcd_init(int port) 213 { 214 /* Set USBH1_STP to GPIO and toggle it */ 215 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO); 216 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD); 217 218 gpio_direction_output(MX51EVK_USBH1_STP, 0); 219 gpio_direction_output(MX51EVK_USB_PHY_RESET, 0); 220 mdelay(10); 221 gpio_set_value(MX51EVK_USBH1_STP, 1); 222 223 /* Set back USBH1_STP to be function */ 224 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); 225 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD); 226 227 /* De-assert USB PHY RESETB */ 228 gpio_set_value(MX51EVK_USB_PHY_RESET, 1); 229 230 /* Drive USB_CLK_EN_B line low */ 231 gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0); 232 233 /* Reset USB hub */ 234 gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0); 235 mdelay(2); 236 gpio_set_value(MX51EVK_USBH1_HUB_RST, 1); 237 return 0; 238 } 239 #endif 240 241 static void power_init(void) 242 { 243 unsigned int val; 244 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; 245 struct pmic *p; 246 247 pmic_init(); 248 p = get_pmic(); 249 250 /* Write needed to Power Gate 2 register */ 251 pmic_reg_read(p, REG_POWER_MISC, &val); 252 val &= ~PWGT2SPIEN; 253 pmic_reg_write(p, REG_POWER_MISC, val); 254 255 /* Externally powered */ 256 pmic_reg_read(p, REG_CHARGE, &val); 257 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; 258 pmic_reg_write(p, REG_CHARGE, val); 259 260 /* power up the system first */ 261 pmic_reg_write(p, REG_POWER_MISC, PWUP); 262 263 /* Set core voltage to 1.1V */ 264 pmic_reg_read(p, REG_SW_0, &val); 265 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; 266 pmic_reg_write(p, REG_SW_0, val); 267 268 /* Setup VCC (SW2) to 1.25 */ 269 pmic_reg_read(p, REG_SW_1, &val); 270 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; 271 pmic_reg_write(p, REG_SW_1, val); 272 273 /* Setup 1V2_DIG1 (SW3) to 1.25 */ 274 pmic_reg_read(p, REG_SW_2, &val); 275 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; 276 pmic_reg_write(p, REG_SW_2, val); 277 udelay(50); 278 279 /* Raise the core frequency to 800MHz */ 280 writel(0x0, &mxc_ccm->cacrr); 281 282 /* Set switchers in Auto in NORMAL mode & STANDBY mode */ 283 /* Setup the switcher mode for SW1 & SW2*/ 284 pmic_reg_read(p, REG_SW_4, &val); 285 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | 286 (SWMODE_MASK << SWMODE2_SHIFT))); 287 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | 288 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); 289 pmic_reg_write(p, REG_SW_4, val); 290 291 /* Setup the switcher mode for SW3 & SW4 */ 292 pmic_reg_read(p, REG_SW_5, &val); 293 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | 294 (SWMODE_MASK << SWMODE4_SHIFT))); 295 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | 296 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); 297 pmic_reg_write(p, REG_SW_5, val); 298 299 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ 300 pmic_reg_read(p, REG_SETTING_0, &val); 301 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); 302 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; 303 pmic_reg_write(p, REG_SETTING_0, val); 304 305 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ 306 pmic_reg_read(p, REG_SETTING_1, &val); 307 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); 308 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; 309 pmic_reg_write(p, REG_SETTING_1, val); 310 311 /* Configure VGEN3 and VCAM regulators to use external PNP */ 312 val = VGEN3CONFIG | VCAMCONFIG; 313 pmic_reg_write(p, REG_MODE_1, val); 314 udelay(200); 315 316 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ 317 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | 318 VVIDEOEN | VAUDIOEN | VSDEN; 319 pmic_reg_write(p, REG_MODE_1, val); 320 321 mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1); 322 gpio_direction_output(46, 0); 323 324 udelay(500); 325 326 gpio_set_value(46, 1); 327 } 328 329 #ifdef CONFIG_FSL_ESDHC 330 int board_mmc_getcd(struct mmc *mmc) 331 { 332 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 333 int ret; 334 335 mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); 336 gpio_direction_input(0); 337 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); 338 gpio_direction_input(6); 339 340 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 341 ret = !gpio_get_value(0); 342 else 343 ret = !gpio_get_value(6); 344 345 return ret; 346 } 347 348 int board_mmc_init(bd_t *bis) 349 { 350 u32 index; 351 s32 status = 0; 352 353 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; 354 index++) { 355 switch (index) { 356 case 0: 357 mxc_request_iomux(MX51_PIN_SD1_CMD, 358 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 359 mxc_request_iomux(MX51_PIN_SD1_CLK, 360 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 361 mxc_request_iomux(MX51_PIN_SD1_DATA0, 362 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 363 mxc_request_iomux(MX51_PIN_SD1_DATA1, 364 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 365 mxc_request_iomux(MX51_PIN_SD1_DATA2, 366 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 367 mxc_request_iomux(MX51_PIN_SD1_DATA3, 368 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 369 mxc_iomux_set_pad(MX51_PIN_SD1_CMD, 370 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 371 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 372 PAD_CTL_PUE_PULL | 373 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 374 mxc_iomux_set_pad(MX51_PIN_SD1_CLK, 375 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 376 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | 377 PAD_CTL_PUE_PULL | 378 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 379 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, 380 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 381 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 382 PAD_CTL_PUE_PULL | 383 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 384 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, 385 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 386 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 387 PAD_CTL_PUE_PULL | 388 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 389 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, 390 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 391 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 392 PAD_CTL_PUE_PULL | 393 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 394 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, 395 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 396 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | 397 PAD_CTL_PUE_PULL | 398 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 399 mxc_request_iomux(MX51_PIN_GPIO1_0, 400 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 401 mxc_iomux_set_pad(MX51_PIN_GPIO1_0, 402 PAD_CTL_HYS_ENABLE); 403 mxc_request_iomux(MX51_PIN_GPIO1_1, 404 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 405 mxc_iomux_set_pad(MX51_PIN_GPIO1_1, 406 PAD_CTL_HYS_ENABLE); 407 break; 408 case 1: 409 mxc_request_iomux(MX51_PIN_SD2_CMD, 410 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 411 mxc_request_iomux(MX51_PIN_SD2_CLK, 412 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 413 mxc_request_iomux(MX51_PIN_SD2_DATA0, 414 IOMUX_CONFIG_ALT0); 415 mxc_request_iomux(MX51_PIN_SD2_DATA1, 416 IOMUX_CONFIG_ALT0); 417 mxc_request_iomux(MX51_PIN_SD2_DATA2, 418 IOMUX_CONFIG_ALT0); 419 mxc_request_iomux(MX51_PIN_SD2_DATA3, 420 IOMUX_CONFIG_ALT0); 421 mxc_iomux_set_pad(MX51_PIN_SD2_CMD, 422 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 423 PAD_CTL_SRE_FAST); 424 mxc_iomux_set_pad(MX51_PIN_SD2_CLK, 425 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 426 PAD_CTL_SRE_FAST); 427 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, 428 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 429 PAD_CTL_SRE_FAST); 430 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, 431 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 432 PAD_CTL_SRE_FAST); 433 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, 434 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 435 PAD_CTL_SRE_FAST); 436 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, 437 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 438 PAD_CTL_SRE_FAST); 439 mxc_request_iomux(MX51_PIN_SD2_CMD, 440 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 441 mxc_request_iomux(MX51_PIN_GPIO1_6, 442 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 443 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, 444 PAD_CTL_HYS_ENABLE); 445 mxc_request_iomux(MX51_PIN_GPIO1_5, 446 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 447 mxc_iomux_set_pad(MX51_PIN_GPIO1_5, 448 PAD_CTL_HYS_ENABLE); 449 break; 450 default: 451 printf("Warning: you configured more ESDHC controller" 452 "(%d) as supported by the board(2)\n", 453 CONFIG_SYS_FSL_ESDHC_NUM); 454 return status; 455 } 456 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 457 } 458 return status; 459 } 460 #endif 461 462 static struct fb_videomode claa_wvga = { 463 .name = "CLAA07LC0ACW", 464 .refresh = 57, 465 .xres = 800, 466 .yres = 480, 467 .pixclock = 37037, 468 .left_margin = 40, 469 .right_margin = 60, 470 .upper_margin = 10, 471 .lower_margin = 10, 472 .hsync_len = 20, 473 .vsync_len = 10, 474 .sync = 0, 475 .vmode = FB_VMODE_NONINTERLACED 476 }; 477 478 void lcd_iomux(void) 479 { 480 /* DI2_PIN15 */ 481 mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4); 482 483 /* Pad settings for MX51_PIN_DI2_DISP_CLK */ 484 mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE | 485 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | 486 PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW); 487 488 /* Turn on 3.3V voltage for LCD */ 489 mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3); 490 gpio_direction_output(MX51EVK_LCD_3V3, 1); 491 492 /* Turn on 5V voltage for LCD */ 493 mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3); 494 gpio_direction_output(MX51EVK_LCD_5V, 1); 495 496 /* Turn on GPIO backlight */ 497 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); 498 mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, 499 INPUT_CTL_PATH1); 500 gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1); 501 } 502 503 void lcd_enable(void) 504 { 505 int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565); 506 if (ret) 507 printf("LCD cannot be configured: %d\n", ret); 508 } 509 510 int board_early_init_f(void) 511 { 512 setup_iomux_uart(); 513 setup_iomux_fec(); 514 #ifdef CONFIG_USB_EHCI_MX5 515 setup_usb_h1(); 516 #endif 517 lcd_iomux(); 518 519 return 0; 520 } 521 522 int board_init(void) 523 { 524 /* address of boot parameters */ 525 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 526 527 lcd_enable(); 528 529 return 0; 530 } 531 532 #ifdef CONFIG_BOARD_LATE_INIT 533 int board_late_init(void) 534 { 535 #ifdef CONFIG_MXC_SPI 536 setup_iomux_spi(); 537 power_init(); 538 #endif 539 setenv("stdout", "serial"); 540 541 return 0; 542 } 543 #endif 544 545 int checkboard(void) 546 { 547 puts("Board: MX51EVK\n"); 548 549 return 0; 550 } 551