1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/mx51_pins.h> 27 #include <asm/arch/iomux.h> 28 #include <asm/errno.h> 29 #include <asm/arch/sys_proto.h> 30 #include <i2c.h> 31 #include <mmc.h> 32 #include <fsl_esdhc.h> 33 #include "mx51evk.h" 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static u32 system_rev; 38 struct io_board_ctrl *mx51_io_board; 39 40 #ifdef CONFIG_FSL_ESDHC 41 struct fsl_esdhc_cfg esdhc_cfg[2] = { 42 {MMC_SDHC1_BASE_ADDR, 1, 1}, 43 {MMC_SDHC2_BASE_ADDR, 1, 1}, 44 }; 45 #endif 46 47 u32 get_board_rev(void) 48 { 49 return system_rev; 50 } 51 52 int dram_init(void) 53 { 54 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 55 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, 56 PHYS_SDRAM_1_SIZE); 57 return 0; 58 } 59 60 static void setup_iomux_uart(void) 61 { 62 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | 63 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; 64 65 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); 66 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); 67 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); 68 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); 69 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); 70 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); 71 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); 72 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); 73 } 74 75 static void setup_expio(void) 76 { 77 u32 reg; 78 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; 79 struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR; 80 81 /* CS5 setup */ 82 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); 83 writel(0x00410089, &pweim[5].csgcr1); 84 writel(0x00000002, &pweim[5].csgcr2); 85 86 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ 87 writel(0x32260000, &pweim[5].csrcr1); 88 89 /* APR = 0 */ 90 writel(0x00000000, &pweim[5].csrcr2); 91 92 /* 93 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, 94 * WCSA=0, WCSN=0 95 */ 96 writel(0x72080F00, &pweim[5].cswcr1); 97 98 mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR + 99 IO_BOARD_OFFSET); 100 if ((readw(&mx51_io_board->id1) == 0xAAAA) && 101 (readw(&mx51_io_board->id2) == 0x5555)) { 102 if (is_soc_rev(CHIP_REV_2_0) < 0) { 103 reg = readl(&pclkctl->cbcdr); 104 reg = (reg & (~0x70000)) | 0x30000; 105 writel(reg, &pclkctl->cbcdr); 106 /* make sure divider effective */ 107 while (readl(&pclkctl->cdhipr) != 0) 108 ; 109 writel(0x0, &pclkctl->ccdr); 110 } 111 } else { 112 /* CS1 */ 113 writel(0x00410089, &pweim[1].csgcr1); 114 writel(0x00000002, &pweim[1].csgcr2); 115 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ 116 writel(0x32260000, &pweim[1].csrcr1); 117 /* APR=0 */ 118 writel(0x00000000, &pweim[1].csrcr2); 119 /* 120 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, 121 * WEN=0, WCSA=0, WCSN=0 122 */ 123 writel(0x72080F00, &pweim[1].cswcr1); 124 mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR + 125 IO_BOARD_OFFSET); 126 } 127 128 /* Reset interrupt status reg */ 129 writew(0x1F, &(mx51_io_board->int_rest)); 130 writew(0x00, &(mx51_io_board->int_rest)); 131 writew(0xFFFF, &(mx51_io_board->int_mask)); 132 133 /* Reset the XUART and Ethernet controllers */ 134 reg = readw(&(mx51_io_board->sw_reset)); 135 reg |= 0x9; 136 writew(reg, &(mx51_io_board->sw_reset)); 137 reg &= ~0x9; 138 writew(reg, &(mx51_io_board->sw_reset)); 139 } 140 141 static void setup_iomux_fec(void) 142 { 143 /*FEC_MDIO*/ 144 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3); 145 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD); 146 147 /*FEC_MDC*/ 148 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); 149 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); 150 151 /* FEC RDATA[3] */ 152 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); 153 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); 154 155 /* FEC RDATA[2] */ 156 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); 157 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); 158 159 /* FEC RDATA[1] */ 160 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); 161 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); 162 163 /* FEC RDATA[0] */ 164 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); 165 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); 166 167 /* FEC TDATA[3] */ 168 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); 169 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); 170 171 /* FEC TDATA[2] */ 172 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); 173 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); 174 175 /* FEC TDATA[1] */ 176 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); 177 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); 178 179 /* FEC TDATA[0] */ 180 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); 181 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); 182 183 /* FEC TX_EN */ 184 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); 185 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); 186 187 /* FEC TX_ER */ 188 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); 189 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); 190 191 /* FEC TX_CLK */ 192 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); 193 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); 194 195 /* FEC TX_COL */ 196 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); 197 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); 198 199 /* FEC RX_CLK */ 200 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); 201 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); 202 203 /* FEC RX_CRS */ 204 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); 205 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); 206 207 /* FEC RX_ER */ 208 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); 209 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); 210 211 /* FEC RX_DV */ 212 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); 213 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); 214 } 215 216 #ifdef CONFIG_FSL_ESDHC 217 int board_mmc_getcd(u8 *cd, struct mmc *mmc) 218 { 219 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 220 221 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 222 *cd = readl(GPIO1_BASE_ADDR) & 0x01; 223 else 224 *cd = readl(GPIO1_BASE_ADDR) & 0x40; 225 226 return 0; 227 } 228 229 int board_mmc_init(bd_t *bis) 230 { 231 u32 index; 232 s32 status = 0; 233 234 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; 235 index++) { 236 switch (index) { 237 case 0: 238 mxc_request_iomux(MX51_PIN_SD1_CMD, 239 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 240 mxc_request_iomux(MX51_PIN_SD1_CLK, 241 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 242 mxc_request_iomux(MX51_PIN_SD1_DATA0, 243 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 244 mxc_request_iomux(MX51_PIN_SD1_DATA1, 245 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 246 mxc_request_iomux(MX51_PIN_SD1_DATA2, 247 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 248 mxc_request_iomux(MX51_PIN_SD1_DATA3, 249 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 250 mxc_iomux_set_pad(MX51_PIN_SD1_CMD, 251 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 252 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 253 PAD_CTL_PUE_PULL | 254 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 255 mxc_iomux_set_pad(MX51_PIN_SD1_CLK, 256 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 257 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | 258 PAD_CTL_PUE_PULL | 259 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 260 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, 261 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 262 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 263 PAD_CTL_PUE_PULL | 264 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 265 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, 266 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 267 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 268 PAD_CTL_PUE_PULL | 269 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 270 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, 271 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 272 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 273 PAD_CTL_PUE_PULL | 274 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 275 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, 276 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 277 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | 278 PAD_CTL_PUE_PULL | 279 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 280 mxc_request_iomux(MX51_PIN_GPIO1_0, 281 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 282 mxc_iomux_set_pad(MX51_PIN_GPIO1_0, 283 PAD_CTL_HYS_ENABLE); 284 mxc_request_iomux(MX51_PIN_GPIO1_1, 285 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 286 mxc_iomux_set_pad(MX51_PIN_GPIO1_1, 287 PAD_CTL_HYS_ENABLE); 288 break; 289 case 1: 290 mxc_request_iomux(MX51_PIN_SD2_CMD, 291 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 292 mxc_request_iomux(MX51_PIN_SD2_CLK, 293 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 294 mxc_request_iomux(MX51_PIN_SD2_DATA0, 295 IOMUX_CONFIG_ALT0); 296 mxc_request_iomux(MX51_PIN_SD2_DATA1, 297 IOMUX_CONFIG_ALT0); 298 mxc_request_iomux(MX51_PIN_SD2_DATA2, 299 IOMUX_CONFIG_ALT0); 300 mxc_request_iomux(MX51_PIN_SD2_DATA3, 301 IOMUX_CONFIG_ALT0); 302 mxc_iomux_set_pad(MX51_PIN_SD2_CMD, 303 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 304 PAD_CTL_SRE_FAST); 305 mxc_iomux_set_pad(MX51_PIN_SD2_CLK, 306 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 307 PAD_CTL_SRE_FAST); 308 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, 309 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 310 PAD_CTL_SRE_FAST); 311 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, 312 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 313 PAD_CTL_SRE_FAST); 314 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, 315 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 316 PAD_CTL_SRE_FAST); 317 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, 318 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 319 PAD_CTL_SRE_FAST); 320 mxc_request_iomux(MX51_PIN_SD2_CMD, 321 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 322 mxc_request_iomux(MX51_PIN_GPIO1_6, 323 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 324 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, 325 PAD_CTL_HYS_ENABLE); 326 mxc_request_iomux(MX51_PIN_GPIO1_5, 327 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 328 mxc_iomux_set_pad(MX51_PIN_GPIO1_5, 329 PAD_CTL_HYS_ENABLE); 330 break; 331 default: 332 printf("Warning: you configured more ESDHC controller" 333 "(%d) as supported by the board(2)\n", 334 CONFIG_SYS_FSL_ESDHC_NUM); 335 return status; 336 } 337 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 338 } 339 return status; 340 } 341 #endif 342 343 int board_init(void) 344 { 345 system_rev = get_cpu_rev(); 346 347 gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; 348 /* address of boot parameters */ 349 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 350 351 setup_iomux_uart(); 352 setup_expio(); 353 setup_iomux_fec(); 354 return 0; 355 } 356 357 int checkboard(void) 358 { 359 puts("Board: MX51EVK "); 360 361 switch (system_rev & 0xff) { 362 case CHIP_REV_3_0: 363 puts("3.0 ["); 364 break; 365 case CHIP_REV_2_5: 366 puts("2.5 ["); 367 break; 368 case CHIP_REV_2_0: 369 puts("2.0 ["); 370 break; 371 case CHIP_REV_1_1: 372 puts("1.1 ["); 373 break; 374 case CHIP_REV_1_0: 375 default: 376 puts("1.0 ["); 377 break; 378 } 379 380 switch (__raw_readl(SRC_BASE_ADDR + 0x8)) { 381 case 0x0001: 382 puts("POR"); 383 break; 384 case 0x0009: 385 puts("RST"); 386 break; 387 case 0x0010: 388 case 0x0011: 389 puts("WDOG"); 390 break; 391 default: 392 puts("unknown"); 393 } 394 puts("]\n"); 395 return 0; 396 } 397