1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx51_pins.h>
27 #include <asm/arch/iomux.h>
28 #include <asm/errno.h>
29 #include <asm/arch/sys_proto.h>
30 #include <i2c.h>
31 #include <mmc.h>
32 #include <fsl_esdhc.h>
33 #include "mx51evk.h"
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 static u32 system_rev;
38 struct io_board_ctrl *mx51_io_board;
39 
40 #ifdef CONFIG_FSL_ESDHC
41 struct fsl_esdhc_cfg esdhc_cfg[2] = {
42 	{MMC_SDHC1_BASE_ADDR, 1, 1},
43 	{MMC_SDHC2_BASE_ADDR, 1, 1},
44 };
45 #endif
46 
47 u32 get_board_rev(void)
48 {
49 	return system_rev;
50 }
51 
52 int dram_init(void)
53 {
54 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
55 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
56 			PHYS_SDRAM_1_SIZE);
57 	return 0;
58 }
59 
60 static void setup_iomux_uart(void)
61 {
62 	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
63 			PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
64 
65 	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
66 	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
67 	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
68 	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
69 	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
70 	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
71 	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
72 	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
73 }
74 
75 static void setup_iomux_fec(void)
76 {
77 	/*FEC_MDIO*/
78 	mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
79 	mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
80 
81 	/*FEC_MDC*/
82 	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
83 	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
84 
85 	/* FEC RDATA[3] */
86 	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
87 	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
88 
89 	/* FEC RDATA[2] */
90 	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
91 	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
92 
93 	/* FEC RDATA[1] */
94 	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
95 	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
96 
97 	/* FEC RDATA[0] */
98 	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
99 	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
100 
101 	/* FEC TDATA[3] */
102 	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
103 	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
104 
105 	/* FEC TDATA[2] */
106 	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
107 	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
108 
109 	/* FEC TDATA[1] */
110 	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
111 	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
112 
113 	/* FEC TDATA[0] */
114 	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
115 	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
116 
117 	/* FEC TX_EN */
118 	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
119 	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
120 
121 	/* FEC TX_ER */
122 	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
123 	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
124 
125 	/* FEC TX_CLK */
126 	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
127 	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
128 
129 	/* FEC TX_COL */
130 	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
131 	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
132 
133 	/* FEC RX_CLK */
134 	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
135 	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
136 
137 	/* FEC RX_CRS */
138 	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
139 	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
140 
141 	/* FEC RX_ER */
142 	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
143 	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
144 
145 	/* FEC RX_DV */
146 	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
147 	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
148 }
149 
150 #ifdef CONFIG_FSL_ESDHC
151 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
152 {
153 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
154 
155 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
156 		*cd = readl(GPIO1_BASE_ADDR) & 0x01;
157 	else
158 		*cd = readl(GPIO1_BASE_ADDR) & 0x40;
159 
160 	return 0;
161 }
162 
163 int board_mmc_init(bd_t *bis)
164 {
165 	u32 index;
166 	s32 status = 0;
167 
168 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
169 			index++) {
170 		switch (index) {
171 		case 0:
172 			mxc_request_iomux(MX51_PIN_SD1_CMD,
173 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
174 			mxc_request_iomux(MX51_PIN_SD1_CLK,
175 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
176 			mxc_request_iomux(MX51_PIN_SD1_DATA0,
177 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
178 			mxc_request_iomux(MX51_PIN_SD1_DATA1,
179 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
180 			mxc_request_iomux(MX51_PIN_SD1_DATA2,
181 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
182 			mxc_request_iomux(MX51_PIN_SD1_DATA3,
183 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
184 			mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
185 				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
186 				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
187 				PAD_CTL_PUE_PULL |
188 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
189 			mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
190 				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
191 				PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
192 				PAD_CTL_PUE_PULL |
193 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
194 			mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
195 				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
196 				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
197 				PAD_CTL_PUE_PULL |
198 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
199 			mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
200 				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
201 				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
202 				PAD_CTL_PUE_PULL |
203 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
204 			mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
205 				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
206 				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
207 				PAD_CTL_PUE_PULL |
208 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
209 			mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
210 				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
211 				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
212 				PAD_CTL_PUE_PULL |
213 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
214 			mxc_request_iomux(MX51_PIN_GPIO1_0,
215 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
216 			mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
217 				PAD_CTL_HYS_ENABLE);
218 			mxc_request_iomux(MX51_PIN_GPIO1_1,
219 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
220 			mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
221 				PAD_CTL_HYS_ENABLE);
222 			break;
223 		case 1:
224 			mxc_request_iomux(MX51_PIN_SD2_CMD,
225 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
226 			mxc_request_iomux(MX51_PIN_SD2_CLK,
227 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
228 			mxc_request_iomux(MX51_PIN_SD2_DATA0,
229 				IOMUX_CONFIG_ALT0);
230 			mxc_request_iomux(MX51_PIN_SD2_DATA1,
231 				IOMUX_CONFIG_ALT0);
232 			mxc_request_iomux(MX51_PIN_SD2_DATA2,
233 				IOMUX_CONFIG_ALT0);
234 			mxc_request_iomux(MX51_PIN_SD2_DATA3,
235 				IOMUX_CONFIG_ALT0);
236 			mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
237 				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
238 				PAD_CTL_SRE_FAST);
239 			mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
240 				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
241 				PAD_CTL_SRE_FAST);
242 			mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
243 				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
244 				PAD_CTL_SRE_FAST);
245 			mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
246 				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
247 				PAD_CTL_SRE_FAST);
248 			mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
249 				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
250 				PAD_CTL_SRE_FAST);
251 			mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
252 				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
253 				PAD_CTL_SRE_FAST);
254 			mxc_request_iomux(MX51_PIN_SD2_CMD,
255 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
256 			mxc_request_iomux(MX51_PIN_GPIO1_6,
257 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
258 			mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
259 				PAD_CTL_HYS_ENABLE);
260 			mxc_request_iomux(MX51_PIN_GPIO1_5,
261 				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
262 			mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
263 				PAD_CTL_HYS_ENABLE);
264 			break;
265 		default:
266 			printf("Warning: you configured more ESDHC controller"
267 				"(%d) as supported by the board(2)\n",
268 				CONFIG_SYS_FSL_ESDHC_NUM);
269 			return status;
270 		}
271 		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
272 	}
273 	return status;
274 }
275 #endif
276 
277 int board_init(void)
278 {
279 	system_rev = get_cpu_rev();
280 
281 	gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
282 	/* address of boot parameters */
283 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
284 
285 	setup_iomux_uart();
286 	setup_iomux_fec();
287 	return 0;
288 }
289 
290 int checkboard(void)
291 {
292 	puts("Board: MX51EVK ");
293 
294 	switch (system_rev & 0xff) {
295 	case CHIP_REV_3_0:
296 		puts("3.0 [");
297 		break;
298 	case CHIP_REV_2_5:
299 		puts("2.5 [");
300 		break;
301 	case CHIP_REV_2_0:
302 		puts("2.0 [");
303 		break;
304 	case CHIP_REV_1_1:
305 		puts("1.1 [");
306 		break;
307 	case CHIP_REV_1_0:
308 	default:
309 		puts("1.0 [");
310 		break;
311 	}
312 
313 	switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
314 	case 0x0001:
315 		puts("POR");
316 		break;
317 	case 0x0009:
318 		puts("RST");
319 		break;
320 	case 0x0010:
321 	case 0x0011:
322 		puts("WDOG");
323 		break;
324 	default:
325 		puts("unknown");
326 	}
327 	puts("]\n");
328 	return 0;
329 }
330