1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/gpio.h> 26 #include <asm/arch/imx-regs.h> 27 #include <asm/arch/mx5x_pins.h> 28 #include <asm/arch/iomux.h> 29 #include <asm/errno.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/arch/crm_regs.h> 32 #include <i2c.h> 33 #include <mmc.h> 34 #include <fsl_esdhc.h> 35 #include <pmic.h> 36 #include <fsl_pmic.h> 37 #include <mc13892.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 static u32 system_rev; 42 43 #ifdef CONFIG_FSL_ESDHC 44 struct fsl_esdhc_cfg esdhc_cfg[2] = { 45 {MMC_SDHC1_BASE_ADDR, 1}, 46 {MMC_SDHC2_BASE_ADDR, 1}, 47 }; 48 #endif 49 50 u32 get_board_rev(void) 51 { 52 return system_rev; 53 } 54 55 int dram_init(void) 56 { 57 /* dram_init must store complete ramsize in gd->ram_size */ 58 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 59 PHYS_SDRAM_1_SIZE); 60 return 0; 61 } 62 63 static void setup_iomux_uart(void) 64 { 65 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | 66 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; 67 68 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); 69 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); 70 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); 71 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); 72 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); 73 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); 74 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); 75 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); 76 } 77 78 static void setup_iomux_fec(void) 79 { 80 /*FEC_MDIO*/ 81 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3); 82 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD); 83 84 /*FEC_MDC*/ 85 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); 86 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); 87 88 /* FEC RDATA[3] */ 89 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); 90 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); 91 92 /* FEC RDATA[2] */ 93 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); 94 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); 95 96 /* FEC RDATA[1] */ 97 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); 98 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); 99 100 /* FEC RDATA[0] */ 101 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); 102 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); 103 104 /* FEC TDATA[3] */ 105 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); 106 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); 107 108 /* FEC TDATA[2] */ 109 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); 110 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); 111 112 /* FEC TDATA[1] */ 113 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); 114 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); 115 116 /* FEC TDATA[0] */ 117 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); 118 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); 119 120 /* FEC TX_EN */ 121 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); 122 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); 123 124 /* FEC TX_ER */ 125 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); 126 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); 127 128 /* FEC TX_CLK */ 129 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); 130 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); 131 132 /* FEC TX_COL */ 133 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); 134 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); 135 136 /* FEC RX_CLK */ 137 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); 138 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); 139 140 /* FEC RX_CRS */ 141 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); 142 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); 143 144 /* FEC RX_ER */ 145 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); 146 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); 147 148 /* FEC RX_DV */ 149 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); 150 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); 151 } 152 153 #ifdef CONFIG_MXC_SPI 154 static void setup_iomux_spi(void) 155 { 156 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ 157 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); 158 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105); 159 160 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ 161 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); 162 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105); 163 164 /* de-select SS1 of instance: ecspi1. */ 165 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); 166 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85); 167 168 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */ 169 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); 170 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185); 171 172 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */ 173 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); 174 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180); 175 176 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ 177 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); 178 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105); 179 } 180 #endif 181 182 static void power_init(void) 183 { 184 unsigned int val; 185 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; 186 struct pmic *p; 187 188 pmic_init(); 189 p = get_pmic(); 190 191 /* Write needed to Power Gate 2 register */ 192 pmic_reg_read(p, REG_POWER_MISC, &val); 193 val &= ~PWGT2SPIEN; 194 pmic_reg_write(p, REG_POWER_MISC, val); 195 196 /* Externally powered */ 197 pmic_reg_read(p, REG_CHARGE, &val); 198 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; 199 pmic_reg_write(p, REG_CHARGE, val); 200 201 /* power up the system first */ 202 pmic_reg_write(p, REG_POWER_MISC, PWUP); 203 204 /* Set core voltage to 1.1V */ 205 pmic_reg_read(p, REG_SW_0, &val); 206 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; 207 pmic_reg_write(p, REG_SW_0, val); 208 209 /* Setup VCC (SW2) to 1.25 */ 210 pmic_reg_read(p, REG_SW_1, &val); 211 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; 212 pmic_reg_write(p, REG_SW_1, val); 213 214 /* Setup 1V2_DIG1 (SW3) to 1.25 */ 215 pmic_reg_read(p, REG_SW_2, &val); 216 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; 217 pmic_reg_write(p, REG_SW_2, val); 218 udelay(50); 219 220 /* Raise the core frequency to 800MHz */ 221 writel(0x0, &mxc_ccm->cacrr); 222 223 /* Set switchers in Auto in NORMAL mode & STANDBY mode */ 224 /* Setup the switcher mode for SW1 & SW2*/ 225 pmic_reg_read(p, REG_SW_4, &val); 226 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | 227 (SWMODE_MASK << SWMODE2_SHIFT))); 228 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | 229 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); 230 pmic_reg_write(p, REG_SW_4, val); 231 232 /* Setup the switcher mode for SW3 & SW4 */ 233 pmic_reg_read(p, REG_SW_5, &val); 234 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | 235 (SWMODE_MASK << SWMODE4_SHIFT))); 236 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | 237 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); 238 pmic_reg_write(p, REG_SW_5, val); 239 240 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ 241 pmic_reg_read(p, REG_SETTING_0, &val); 242 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); 243 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; 244 pmic_reg_write(p, REG_SETTING_0, val); 245 246 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ 247 pmic_reg_read(p, REG_SETTING_1, &val); 248 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); 249 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; 250 pmic_reg_write(p, REG_SETTING_1, val); 251 252 /* Configure VGEN3 and VCAM regulators to use external PNP */ 253 val = VGEN3CONFIG | VCAMCONFIG; 254 pmic_reg_write(p, REG_MODE_1, val); 255 udelay(200); 256 257 gpio_direction_output(46, 0); 258 259 /* Reset the ethernet controller over GPIO */ 260 writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); 261 262 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ 263 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | 264 VVIDEOEN | VAUDIOEN | VSDEN; 265 pmic_reg_write(p, REG_MODE_1, val); 266 267 udelay(500); 268 269 gpio_set_value(46, 1); 270 } 271 272 #ifdef CONFIG_FSL_ESDHC 273 int board_mmc_getcd(u8 *cd, struct mmc *mmc) 274 { 275 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 276 277 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 278 *cd = gpio_get_value(0); 279 else 280 *cd = gpio_get_value(6); 281 282 return 0; 283 } 284 285 int board_mmc_init(bd_t *bis) 286 { 287 u32 index; 288 s32 status = 0; 289 290 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; 291 index++) { 292 switch (index) { 293 case 0: 294 mxc_request_iomux(MX51_PIN_SD1_CMD, 295 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 296 mxc_request_iomux(MX51_PIN_SD1_CLK, 297 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 298 mxc_request_iomux(MX51_PIN_SD1_DATA0, 299 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 300 mxc_request_iomux(MX51_PIN_SD1_DATA1, 301 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 302 mxc_request_iomux(MX51_PIN_SD1_DATA2, 303 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 304 mxc_request_iomux(MX51_PIN_SD1_DATA3, 305 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 306 mxc_iomux_set_pad(MX51_PIN_SD1_CMD, 307 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 308 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 309 PAD_CTL_PUE_PULL | 310 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 311 mxc_iomux_set_pad(MX51_PIN_SD1_CLK, 312 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 313 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | 314 PAD_CTL_PUE_PULL | 315 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 316 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, 317 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 318 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 319 PAD_CTL_PUE_PULL | 320 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 321 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, 322 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 323 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 324 PAD_CTL_PUE_PULL | 325 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 326 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, 327 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 328 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 329 PAD_CTL_PUE_PULL | 330 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 331 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, 332 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 333 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | 334 PAD_CTL_PUE_PULL | 335 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 336 mxc_request_iomux(MX51_PIN_GPIO1_0, 337 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 338 mxc_iomux_set_pad(MX51_PIN_GPIO1_0, 339 PAD_CTL_HYS_ENABLE); 340 mxc_request_iomux(MX51_PIN_GPIO1_1, 341 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 342 mxc_iomux_set_pad(MX51_PIN_GPIO1_1, 343 PAD_CTL_HYS_ENABLE); 344 break; 345 case 1: 346 mxc_request_iomux(MX51_PIN_SD2_CMD, 347 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 348 mxc_request_iomux(MX51_PIN_SD2_CLK, 349 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 350 mxc_request_iomux(MX51_PIN_SD2_DATA0, 351 IOMUX_CONFIG_ALT0); 352 mxc_request_iomux(MX51_PIN_SD2_DATA1, 353 IOMUX_CONFIG_ALT0); 354 mxc_request_iomux(MX51_PIN_SD2_DATA2, 355 IOMUX_CONFIG_ALT0); 356 mxc_request_iomux(MX51_PIN_SD2_DATA3, 357 IOMUX_CONFIG_ALT0); 358 mxc_iomux_set_pad(MX51_PIN_SD2_CMD, 359 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 360 PAD_CTL_SRE_FAST); 361 mxc_iomux_set_pad(MX51_PIN_SD2_CLK, 362 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 363 PAD_CTL_SRE_FAST); 364 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, 365 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 366 PAD_CTL_SRE_FAST); 367 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, 368 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 369 PAD_CTL_SRE_FAST); 370 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, 371 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 372 PAD_CTL_SRE_FAST); 373 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, 374 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 375 PAD_CTL_SRE_FAST); 376 mxc_request_iomux(MX51_PIN_SD2_CMD, 377 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 378 mxc_request_iomux(MX51_PIN_GPIO1_6, 379 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 380 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, 381 PAD_CTL_HYS_ENABLE); 382 mxc_request_iomux(MX51_PIN_GPIO1_5, 383 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 384 mxc_iomux_set_pad(MX51_PIN_GPIO1_5, 385 PAD_CTL_HYS_ENABLE); 386 break; 387 default: 388 printf("Warning: you configured more ESDHC controller" 389 "(%d) as supported by the board(2)\n", 390 CONFIG_SYS_FSL_ESDHC_NUM); 391 return status; 392 } 393 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 394 } 395 return status; 396 } 397 #endif 398 399 int board_early_init_f(void) 400 { 401 setup_iomux_uart(); 402 setup_iomux_fec(); 403 404 return 0; 405 } 406 407 int board_init(void) 408 { 409 system_rev = get_cpu_rev(); 410 411 /* address of boot parameters */ 412 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 413 414 return 0; 415 } 416 417 #ifdef BOARD_LATE_INIT 418 int board_late_init(void) 419 { 420 #ifdef CONFIG_MXC_SPI 421 setup_iomux_spi(); 422 power_init(); 423 #endif 424 return 0; 425 } 426 #endif 427 428 int checkboard(void) 429 { 430 puts("Board: MX51EVK\n"); 431 432 return 0; 433 } 434