1 /* 2 * 3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4 * 5 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __BOARD_MX35_3STACK_H 11 #define __BOARD_MX35_3STACK_H 12 13 #define DBG_BASE_ADDR WEIM_CTRL_CS5 14 #define DBG_CSCR_U_CONFIG 0x0000D843 15 #define DBG_CSCR_L_CONFIG 0x22252521 16 #define DBG_CSCR_A_CONFIG 0x22220A00 17 18 #define CCM_CCMR_CONFIG 0x003F4208 19 #define CCM_PDR0_CONFIG 0x00801000 20 21 /* MEMORY SETTING */ 22 #define ESDCTL_0x92220000 0x92220000 23 #define ESDCTL_0xA2220000 0xA2220000 24 #define ESDCTL_0xB2220000 0xB2220000 25 #define ESDCTL_0x82228080 0x82228080 26 27 #define ESDCTL_PRECHARGE 0x00000400 28 29 #define ESDCTL_MDDR_CONFIG 0x007FFC3F 30 #define ESDCTL_MDDR_MR 0x00000033 31 #define ESDCTL_MDDR_EMR 0x02000000 32 33 #define ESDCTL_DDR2_CONFIG 0x007FFC3F 34 #define ESDCTL_DDR2_EMR2 0x04000000 35 #define ESDCTL_DDR2_EMR3 0x06000000 36 #define ESDCTL_DDR2_EN_DLL 0x02000400 37 #define ESDCTL_DDR2_RESET_DLL 0x00000333 38 #define ESDCTL_DDR2_MR 0x00000233 39 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 40 41 #define ESDCTL_DELAY_LINE5 0x00F49F00 42 #endif /* __BOARD_MX35_3STACK_H */ 43